Cartridge connector

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Pinout of 60-pin Famicom consoles and cartridges

This diagram represents a top-down view looking directly into the connector. Pins 01-30 are on the label side of the cartridge, left to right.

      GND -- |01   31| -- +5V
  CPU A11 -> |02   32| <- M2
  CPU A10 -> |03   33| <- CPU A12
   CPU A9 -> |04   34| <- CPU A13
   CPU A8 -> |05   35| <- CPU A14
   CPU A7 -> |06   36| <> CPU D7
   CPU A6 -> |07   37| <> CPU D6
   CPU A5 -> |08   38| <> CPU D5
   CPU A4 -> |09   39| <> CPU D4
   CPU A3 -> |10   40| <> CPU D3
   CPU A2 -> |11   41| <> CPU D2
   CPU A1 -> |12   42| <> CPU D1
   CPU A0 -> |13   43| <> CPU D0
  CPU R/W -> |14   44| <- /ROMSEL (/A15 + /M2)
     /IRQ <- |15   45| <- Audio from 2A03
      GND -- |16   46| -> Audio to RF
  PPU /RD -> |17   47| <- PPU /WR
CIRAM A10 <- |18   48| -> CIRAM /CE
   PPU A6 -> |19   49| <- PPU /A13
   PPU A5 -> |20   50| <- PPU A7
   PPU A4 -> |21   51| <- PPU A8
   PPU A3 -> |22   52| <- PPU A9
   PPU A2 -> |23   53| <- PPU A10
   PPU A1 -> |24   54| <- PPU A11
   PPU A0 -> |25   55| <- PPU A12
   PPU D0 <> |26   56| <- PPU A13
   PPU D1 <> |27   57| <> PPU D7
   PPU D2 <> |28   58| <> PPU D6
   PPU D3 <> |29   59| <> PPU D5
      +5V -- |30   60| <> PPU D4

Pinout of 72-pin NES consoles and cartridges

This diagram represents a top-down view looking directly into the connector. On a front-loader, pins 01-36 are the top side of the connector. Pins 36-01 are on the label side of the cartridge, left to right.

      +5V -- |36   72| -- GND
 CIC toMB <- |35   71| <- CIC CLK
CIC toPak -> |34   70| <- CIC /RST
   PPU D3 <> |33   69| <> PPU D4
   PPU D2 <> |32   68| <> PPU D5
   PPU D1 <> |31   67| <> PPU D6
   PPU D0 <> |30   66| <> PPU D7
   PPU A0 -> |29   65| <- PPU A13
   PPU A1 -> |28   64| <- PPU A12
   PPU A2 -> |27   63| <- PPU A10
   PPU A3 -> |26   62| <- PPU A11
   PPU A4 -> |25   61| <- PPU A9
   PPU A5 -> |24   60| <- PPU A8
   PPU A6 -> |23   59| <- PPU A7
CIRAM A10 <- |22   58| <- PPU /A13
  PPU /RD -> |21   57| -> CIRAM /CE
    EXP 4    |20   56| <- PPU /WR
    EXP 3    |19   55|    EXP 5
    EXP 2    |18   54|    EXP 6
    EXP 1    |17   53|    EXP 7
    EXP 0    |16   52|    EXP 8
     /IRQ <- |15   51|    EXP 9
  CPU R/W -> |14   50| <- /ROMSEL (/A15 + /M2)
   CPU A0 -> |13   49| <> CPU D0
   CPU A1 -> |12   48| <> CPU D1
   CPU A2 -> |11   47| <> CPU D2
   CPU A3 -> |10   46| <> CPU D3
   CPU A4 -> |09   45| <> CPU D4
   CPU A5 -> |08   44| <> CPU D5
   CPU A6 -> |07   43| <> CPU D6
   CPU A7 -> |06   42| <> CPU D7
   CPU A8 -> |05   41| <- CPU A14
   CPU A9 -> |04   40| <- CPU A13
  CPU A10 -> |03   39| <- CPU A12
  CPU A11 -> |02   38| <- M2
      GND -- |01   37| <- SYSTEM CLK

Additional pinout notes

  • For the Famicom: most chips and components appear on the opposite side of the PCB from the label in Famicom cartridges.
  • For the NES: most chips and components appear on the label side of the PCB in NES cartridges.
  • Active-Low signals are indicated by a / (slash) symbol.
  • The NES and Famicom connectors have a similar arrangement; the connector on the NES is mostly a mirror image of the Famicom's.
  • Most cartridge PCBs made by Nintendo are numbered the same way as indicated in these diagrams.

Signal descriptions

  • +5V : 5V Power supply from the main voltage regulator.
  • GND : 0V power supply.
  • SYSTEM CLK : Main oscillator frequency output. It is only available on 72-pin connectors, and its speed varies between NTSC (21MHz) and PAL (27MHz) machines.
  • M2 : Also called PHI2 (φ2) in official docs (however, see the CPU M2 and CLK description for additional details). This is the CPU clock output. When this signal is high, this means the CPU bus address and data lines are in a stable state and can be latched by external hardware. On reads, the data must be stable until this signal goes low.
  • CPU R/W : The Read/Write signal output from the CPU. This signal is high on during CPU reads and low during CPU writes (switches from one mode to another only when M2 is low).
  • CPU A0..A14 : Also called just A0..A14 in official docs, or CPU A0..A14 (to not confuse with address outputs of mappers sharing the same number). This is the CPU address bus. It is stable when M2 is high. Note that A15 exists, but is not directly available on the connector.
  • CPU D0..D7 : Also called just D0..D7 in official docs, or CPU D0..D7. This is the CPU bidirectional data bus. It goes high impedance on reads, allowing external memory chips to place their data here.
  • /ROMSEL: This pin outputs the logical NAND of M2 and CPU A15. It is low when the CPU reads or writes to $8000-$FFFF and when the address is stable, allowing to enable ROM chips directly. Advanced mappers use more logic between this pin and the actual PRG /CE (to avoid bus conflicts, for example). Using this signal is the only way to determine the state of A15, so it's needed for any mappers doing any address decoding.
  • /IRQ : Interrupt request input. Pull low to trigger an interrupt to the CPU. Can only be connected to an open collector cartridge output (there is an internal pull-up resistor in the NES/Famicom). Can be left floating if interrupts aren't used.
  • Audio from 2A03 : Audio output from the 2A03's sound generation hardware, already amplified. Only exists with 60-pins connectors.
  • Audio to RF : Usually just tied to the audio from 2A03. This one goes directly to the sound output of the console. This allows cartridges to mix audio with their own audio sources. This is not directly present on 72-pins connectors.
  • EXP0..9 : Pins that goes to the expansion port on the bottom of the NES units (not present on Famicoms). Have various uses.
    • EXP 0 : Used by CopyNES in its cartridge reprogramming mode.
    • EXP 2 : Used by some Famicom to NES converters as audio input, because this pin is just straight ahead of the Audio In pin. The NES has to be modified to mix that with the normal audio.
    • EXP 5 : Used by MMC5 cartridges as an open emitter input to the cartridge. Pulling this pin high will force the PRG RAM to be transparent to all reads from it, bypassing any state of the MMC5. Writes aren't disabled in this mode, though. Leave this pin unconnected or tie it to ground will have the PRG RAM working normally (MMC5 carts have their internal pull-down resistor). Only a device that plugs in the expansion port under the NES could make an use of this pin.
    • EXP 6 : Used by the PowerPak and by MMC5 cartridges for expansion audio. A device that plugs into the expansion port under the NES could allow these cartridge to use expansion audio on a NES without using a screwdriver.
    • EXP 9 : Top-loader users wishing to audio-mod for PowerPak expansion audio will often bridge EXP6 to EXP9, because EXP6 is missing on that model NES.
  • PPU /WR : Also called /WE in official docs. This signal is low when the PPU is writing. On its falling edge, the address and data are stable.
  • PPU /RD : Also called /RD in official docs. This signal is low when the PPU is reading. On its falling edge, the address is stable, and the data should be stable until its rising edge.
  • PPU A0..A13 : Also called PA0..13 in official docs. This is the PPU's address bus. Most boards tie PA13 directly to the /CE of CHR ROM or CHR RAM to map it into pattern table space ($0000-$1FFF) without any extra logic.
  • PPU D0..D7 : Also called PD0..7 in official documentation. This is the PPU's bidirectional data bus. Goes high impedance when PPU /RD goes low allowing memory devices to place their data here.
  • PPU /A13 : The inverted form of PPU A13. Typically used to map nametables and attribute tables to $2000-$3FFF.
  • CIRAM /CE : Also called VRAM /CS. This signal is used as an input to enable the internal 2k of VRAM (used for name table and attribute tables typically, but could be made for another use). This signal is usually directly connected with PPU /A13, but carts using their own RAM for name table and attribute tables will have their own logic implemented.
  • CIRAM A10 : Also called VRAM A10. This is the 1k bank selection input for internal VRAM. This is used to control how the name tables are banked; in other words, this selects nametable mirroring. Connect to PPU A10 for vertical mirroring or PPU A11 for horizontal mirroring. Connect it to a software operated latch to allow bank switching of two separate name tables in single-screen mirroring (as in AxROM). Many mappers have software operated mirroring selection: they multiplex PPU A10 and PPU A11 into this pin, selected by a latch.