INES Mapper 168
- PRG ROM size: 64 KiB
- PRG ROM bank size: 16 KiB
- PRG RAM: No
- CHR capacity: 64 KiB RAM, half (or all) battery-backed.
- CHR bank size: 4 KiB
- Nametable mirroring: Hardwired vertical mirroring
- Subject to bus conflicts: no
- CPU $8000-$BFFF: 16 KiB switchable PRG ROM bank
- CPU $C000-$FFFF: 16 KiB PRG ROM bank, fixed to the last bank
- PPU $0000-$0FFF: 4 KiB CHR RAM bank, fixed to the first bank, but see notes in Hardware.
- PPU $1000-$1FFF: 4 KiB switchable CHR RAM bank
- J1: force deselect SRAM U1 when +5V fails
- J2: allow SRAM U1 to remain selected after +5V fails
- J3: Power SRAM U1 from +5V line
- J4: Power SRAM U1 from battery-backed supply
SRAM U2 is always protected and battery-backed.
J1+J4 vs J2+J3 should be selected as a pair. This modification allows 64kB of battery-backed memory.
To the best of our knowledge (5 samples), all delivered boards had J2+J3 selected.
Bank Select ($8000-$BFFF)
7 bit 0 ---- ---- PPxx CCCC || |||| || ++++- Select 4 KB CHR RAM bank for PPU $1000-$1FFF ++-------- Select 16 KB PRG ROM bank for CPU $8000-$BFFF
RAM Protection and IRQ acknowledge ($C000-$FFFF)
15 11 address 0 7 data 0 ---- ---- ---- ---- ---- ---- 11.. .... Y... .... XXXX XZXX | |||| |||| +----------++++-++++- Write 1 then 0 to deprotect SRAM and reset timer = acknowledge interrupt
Only one of the 9 above bits is used, but the software has no a priori reason to know which. The firmware thus writes $FF to $F080 and $00 to $F000. The PCBs were originally laid out to use the bit above marked "Y" (A7).
It is believed that this is also the interrupt acknowledge/counter reset.
To the best of our knowledge (5 samples), all delivered boards were modified to instead use the bit labeled "Z" (D2)
The interrupt is implemented with a large binary counter which drives the /IRQ line low after 1024 M2 cycles. Because the counter continues counting, it will automatically acknowledge itself after another 1024 M2 cycles (for a net frequency of no lower than 874 Hz). In practice, nocash says that the software requires at least 27 IRQs per vblank (for a spacing of not more than 1104 M2 cycles), and the software reliably clears the counter within 30 cycles.
A board could have the resistor placed in the adjacent position, which would choose a delay of 2048 M2 cycles instead, but to the best of our knowledge (5 samples), none were.
Unlike CPROM or iNES Mapper 180, which use AND logic to fix the first bank to 0 and switch the upper bank, the CHR-RAM here instead uses NAND logic, where the CHR banks are the 2's complement of those specified above. Because nothing else can read or write the RAMs except through this interface, the only question is whether the fixed bank is normally battery backed. It is NOT. The difference between NAND and AND logic is invisible to the software, and so emulators could use either convention if exchange of save files between emulators is not anticipated.
It is of casual interest, but also completely irrelevant, that the lower bits of the CHR bank register are out of order: 3012. Once again, because nothing else can read or write the RAMs except through this bank register, this only could matter if one were to desolder the RAMs to read them.
There is a space on the PCB to accept a donor CIC, labelled U11. In editions released before the top-loading NES-101, this space was populated with a Tengen CIC.