INES Mapper 206
|Company||Namco, Tengen, others|
|Games||39 in NesCartDB|
|PRG ROM capacity||128K|
|PRG ROM window||8K + 8K + 16K fixed|
|PRG RAM capacity||None|
|CHR window||2Kx2 + 1Kx4|
|Nametable mirroring||Fixed H/V, or 4|
|iNES mappers||206, 76, 88, 154, 95|
Chips used include "Tengen MIMIC-1" and "Namcot 118", and the boards made by Nintendo of America that used this mapper are NES-DxROM. Many ROMS using this mapper are incorrectly listed as using MMC3, but will usually work if emulated with MMC3, and the mirroring is correct, as if they were on a TEROM or TFROM board.
Compared to MMC3:
- There are no IRQs
- There is no WRAM support
- PRG always has the last two 8KiB banks fixed to the end.
- CHR always gives the left pattern table (0000-0FFF) the two 2KiB banks, and the right pattern table (1000-1FFF) the four 1KiB banks.
- Mirroring is hardwired, one game uses 4-screen mirroring (Gauntlet, DRROM).
- CHR size limit is 64KiB, PRG size limit is 128KiB.
- There are no control registers in the $A000-$FFFF range.
- Naruko observed a bug where writes to RAM (i.e. $0000-$1FFF) while executing code from $8000-$9FFF will cause erratic mapper writes. It is not known whether all five ICs (108, 109, 118, 119, MIMIC-1) have this same bug.
Register mask: $E001
Bank select ($8000-$9FFE, even)
7 bit 0 ---- ---- xxxx xRRR ||| +++- Specify which bank register to update on next write to Bank Data register 0: Select 2 KB CHR bank at PPU $0000-$07FF 1: Select 2 KB CHR bank at PPU $0800-$0FFF 2: Select 1 KB CHR bank at PPU $1000-$13FF 3: Select 1 KB CHR bank at PPU $1400-$17FF 4: Select 1 KB CHR bank at PPU $1800-$1BFF 5: Select 1 KB CHR bank at PPU $1C00-$1FFF 6: Select 8 KB PRG ROM bank at $8000-$9FFF 7: Select 8 KB PRG ROM bank at $A000-$BFFF
See MMC3 and note the absence of any control bits in the upper five bits of this register.
Bank data ($8001-$9FFF, odd)
7 bit 0 ---- ---- xxdd DDDd || |||| ++-++++- New bank value, based on last value written to bank select register (mentioned above)
Only five bits exist for the two 2 KiB CHR banks, only six bits exist for the four 1 KiB CHR banks, and only four bits exist for the two 8 KiB PRG banks.
The game Babel no Tou, on the PCB 3401, is the only game with 32 KiB PRG that allows—and uses!—PRG banking. All other games with 32 KiB PRG connect CPU A13 and CPU A14 directly to the PRG ROM, but fortunately they initialize their PRG registers to work on a normal board. Because all six games can be correctly emulated by respecting the PRG banking registers, it seems no submapper needs to be allocated for this variation.
Mapper 76 increases CHR to 128KiB by inflating the 1KiB CHR banks to 2KiB and making the originally-2KiB banks inaccessible.
Mapper 88 increases CHR to 128KiB by connecting PPU's A12 line to the CHR ROM's A16 line, making tiles in $0000 and $1000 come from disjoint sections of ROM. Because an undersize ROM on a mapper 88 board behaves identically to mapper 206, emulators may treat these mapper numbers as synonymous.
Mapper 154 starts with mapper 88, then adds mapper-controlled one-screen mirroring.
- FCEUX's implementation
- Enri's reverse-engineered schematic of PCBs 3407 and 3416: http://www43.tok2.com/home/cmpslv/Famic/Fcmp206.htm
- Naruko's forum thread about mapper register range