MMC5

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MMC5
ExROM
Company Nintendo, Koei, others
Games 15 in NesCartDB
Complexity ASIC
Boards EKROM, ELROM,
ETROM, EWROM
Pinout MMC5 pinout
PRG ROM capacity 1024K
PRG ROM window 8K, 16K, or 32K
PRG RAM capacity 128K
PRG RAM window 8K ($6000-$DFFF),
16K (only $8000-$BFFF
at PRG mode 1/2)
CHR capacity 1024K
CHR window 1K, 2K, 4K, or 8K
Nametable mirroring arbitrary, up to 3 source
nametables (plus fill mode)
Bus conflicts No
IRQ Yes
Audio Yes
iNES mappers 005

The Nintendo MMC5 is a mapper ASIC used in Nintendo's ExROM Game Pak boards. All MMC5 boards are assigned to mapper 5.

Example games:

  • Castlevania 3
  • Just Breed
  • Uncharted Waters
  • Romance of the Three Kingdoms II
  • Laser Invasion
  • Metal Slader Glory
  • Uchuu Keibitai SDF
  • Shin 4 Nin Uchi Mahjong - Yakuman Tengoku
  • Bandit Kings of Ancient China

The first game to use this chip (Nobunaga's Ambition II) was released in February 1990. The date codes on components on early released cartridges show that manufacturing had started at the end of 1989.

Contents

Overview

The MMC5 is the most powerful mapper ASIC Nintendo made for the NES and Famicom.

It supports many advanced features, including:

  • 4 PRG ROM switching modes
  • 4 CHR ROM switching modes
  • Up to 128KB of WRAM, mappable not only at $6000-$7FFF but also within $8000-$DFFF
    • Supports either one chip (up to 128KB) or two chips (up to 32KB each)
  • An 8 bit by 8 bit multiplier with a 16 bit result for performing quick calculations
  • Scanline detection with counter and configurable IRQ
  • Frame detection with status bit
  • The ability to use different CHR banks for background and 8x16 sprites (allowing 256 unique 8x16 sprite tiles, independent of the background).
  • 1024 bytes of on-chip memory, which can be used for 4 different purposes:
    • An extra general-use nametable
    • Attribute and tile index expansion - address 16384 background tiles at once, and allow each individual 8x8 tile to have its own palette setting
    • Vertical split-screen
    • Extra RAM for storing program variables
  • Three extra sound channels
    • Two pulse channels, identical to those in the NES APU (except lacking pitch sweeps).
    • An 8-bit RAW PCM channel
  • A 'fill mode' nametable, which can be instantly set to contain a specific tile in a specific color (useful for screen transitions)
  • System reset detection
    • Triggered by a positive or negative gap in M2 of at least 11.2 usec.
    • Also triggered and latched by absence of AVcc.
    • After reapplying AVcc, another gap in M2 is sometimes necessary to clear the latch.
    • This feature resets some, but not all, states of the MMC5.
    • The PRG RAM +CE pin is a direct reflection of system reset detection state.

Banks

The MMC5 provides 4 distinct banking modes for both PRG ROM and CHR ROM.

PRG mode 0

  • CPU $6000-$7FFF: 8 KB switchable PRG RAM bank
  • CPU $8000-$FFFF: 32 KB switchable PRG ROM bank

PRG mode 1

  • CPU $6000-$7FFF: 8 KB switchable PRG RAM bank
  • CPU $8000-$BFFF: 16 KB switchable PRG ROM/RAM bank
  • CPU $C000-$FFFF: 16 KB switchable PRG ROM bank

PRG mode 2

  • CPU $6000-$7FFF: 8 KB switchable PRG RAM bank
  • CPU $8000-$BFFF: 16 KB switchable PRG ROM/RAM bank
  • CPU $C000-$DFFF: 8 KB switchable PRG ROM/RAM bank
  • CPU $E000-$FFFF: 8 KB switchable PRG ROM bank

PRG mode 3

  • CPU $6000-$7FFF: 8 KB switchable PRG RAM bank
  • CPU $8000-$9FFF: 8 KB switchable PRG ROM/RAM bank
  • CPU $A000-$BFFF: 8 KB switchable PRG ROM/RAM bank
  • CPU $C000-$DFFF: 8 KB switchable PRG ROM/RAM bank
  • CPU $E000-$FFFF: 8 KB switchable PRG ROM bank

CHR mode 0

  • PPU $0000-$1FFF: 8 KB switchable CHR bank

CHR mode 1

  • PPU $0000-$0FFF: 4 KB switchable CHR bank
  • PPU $1000-$1FFF: 4 KB switchable CHR bank

CHR mode 2

  • PPU $0000-$07FF: 2 KB switchable CHR bank
  • PPU $0800-$0FFF: 2 KB switchable CHR bank
  • PPU $1000-$17FF: 2 KB switchable CHR bank
  • PPU $1800-$1FFF: 2 KB switchable CHR bank

CHR mode 3

  • PPU $0000-$03FF: 1 KB switchable CHR bank
  • PPU $0400-$07FF: 1 KB switchable CHR bank
  • PPU $0800-$0BFF: 1 KB switchable CHR bank
  • PPU $0C00-$0FFF: 1 KB switchable CHR bank
  • PPU $1000-$13FF: 1 KB switchable CHR bank
  • PPU $1400-$17FF: 1 KB switchable CHR bank
  • PPU $1800-$1BFF: 1 KB switchable CHR bank
  • PPU $1C00-$1FFF: 1 KB switchable CHR bank

Registers

Sound

For details on sound operation, see MMC5 audio

NES internal state monitoring

All of these registers overlay various registers that are already used inside the NES, and are fully decoded. A game could write to a mirror of a PPU register to get the MMC5 out of sync, but it's not clear how that could be useful.

8x16 mode enable 1 ($2000 = PPUCTRL)

7  bit  0
---- ----
xxZx xxxx
  |
  +------- Sprite size (0: 8x8 pixels; 1: 8x16 pixels)

8x16 mode enable 2 ($2001 = PPUMASK)

7  bit  0
---------
xxxE Exxx
   | |
   +-+--- 1,2,3: Rendering enabled; 0: rendering disabled

Only when Z is set and at least one E bit is set does the MMC5 draw 8x16 sprites from eight independent banks.[1]

Unknown ($2002 = PPUSTATUS, read only)

Power analysis has detected that both revisions of the MMC5 monitor reads here, purpose unknown.

Unknown ($2005 = PPUSCROLL)

Power analysis has detected that both revisions of the MMC5 monitor writes here, purpose unknown.

Unknown ($2006 = PPUADDR, MMC5A only)

Power analysis has detected that the MMC5A monitors writes here, purpose unknown.

Unknown ($4014 = OAMDMA)

Power analysis has detected that both revisions of the MMC5 monitor writes here, purpose unknown.

Configuration

PRG mode ($5100)

7  bit  0
---- ----
xxxx xxPP
       ||
       ++- Select PRG banking mode
  • 0 - One 32KB bank
  • 1 - Two 16KB banks
  • 2 - One 16KB bank ($8000-$BFFF) and two 8KB banks ($C000-$DFFF and $E000-$FFFF)
  • 3 - Four 8KB banks

Castlevania III uses mode 2, which is similar to VRC6 PRG banking. All other games use mode 3. The Koei games never write to this register, apparently relying on the MMC5 defaulting to mode 3 at power on.

CHR mode ($5101)

7  bit  0
---- ----
xxxx xxCC
       ||
       ++- Select CHR banking mode
  • 0 - 8KB CHR pages
  • 1 - 4KB CHR pages
  • 2 - 2KB CHR pages
  • 3 - 1KB CHR pages

Metal Slader Glory uses 4KB CHR pages. All other games use 1KB pages.

PRG RAM Protect 1 ($5102)

7  bit  0
---- ----
xxxx xxWW
       ||
       ++- RAM protect 1

In order to enable writing to PRG RAM, this must be set to binary '10' (e.g. $02).

PRG RAM Protect 2 ($5103)

7  bit  0
---- ----
xxxx xxWW
       ||
       ++- RAM protect 2

In order to enable writing to PRG RAM, this must be set to binary '01' (e.g. $01).

Extended RAM mode ($5104)

7  bit  0
---- ----
xxxx xxXX
       ||
       ++- Specify extended RAM usage
  • 0 - Use as extra nametable (possibly for split mode)
  • 1 - Use as extended attribute data (can also be used as extended nametable)
  • 2 - Use as ordinary RAM
  • 3 - Use as ordinary RAM, write protected

Nametable mapping ($5105)

7  bit  0
---- ----
DDCC BBAA
|||| ||||
|||| ||++- Select nametable at PPU $2000-$23FF
|||| ++--- Select nametable at PPU $2400-$27FF
||++------ Select nametable at PPU $2800-$2BFF
++-------- Select nametable at PPU $2C00-$2FFF

Nametable values:

  • 0 - On-board VRAM page 0
  • 1 - On-board VRAM page 1
  • 2 - Internal Expansion RAM, only if the Extended RAM mode allows it ($5104 is 00/01); otherwise, the nametable will read as all zeros,
  • 3 - Fill-mode data

Mirroring examples:

Mode Value NTD NTC NTB NTA
Horizontal $50  %01  %01  %00  %00
Vertical $44  %01  %00  %01  %00
Single-screen CIRAM 0 $00  %00  %00  %00  %00
Single-screen CIRAM 1 $55  %01  %01  %01  %01
Single-screen ExRAM $AA  %10  %10  %10  %10
Single-Screen Fill-mode $FF  %11  %11  %11  %11
Diagonal $14  %00  %01  %01  %00

Fill-mode tile ($5106)

 All eight bits specify the tile number to use for fill-mode nametable

Fill-mode color ($5107)

7  bit  0
---- ----
xxxx xxAA
       ||
       ++- Specify attribute bits to use for fill-mode nametable

PRG Bankswitching ($5113-$5117)

In general, when the CPU accesses an address that corresponds to the range of a PRG bank designated by the present PRG mode, the bits of that PRG bank register are applied to the appropriate PRG address buses as follows:

7  bit  0
---- ----
RAAA AaAA
|||| ||||
|||| |||+- PRG ROM/RAM A13
|||| ||+-- PRG ROM/RAM A14
|||| |+--- PRG ROM/RAM A15, also selecting between PRG RAM /CE 0 and 1
|||| +---- PRG ROM/RAM A16
|||+------ PRG ROM A17
||+------- PRG ROM A18
|+-------- PRG ROM A19
+--------- RAM/ROM toggle (0: RAM; 1: ROM) (registers $5114-$5116 only)

Conceptual bank register effective areas versus PRG mode:

CPU memory affected for each mode (see #PRG mode ($5100))
Register Mode 3 Range Mode 2 Range Mode 1 Range Mode 0 Range
$5113 $6000-$7FFF (RAM) $6000-$7FFF (RAM) $6000-$7FFF (RAM) $6000-$7FFF (RAM)
$5114 $8000-$9FFF v (none) v v (none) v v (none) v
$5115 $A000-$BFFF $8000-$BFFF $8000-$BFFF v (none) v
$5116 $C000-$DFFF $C000$-DFFF v (none) v v (none) v
$5117 $E000-$FFFF (ROM) $E000-$FFFF (ROM) $C000-$FFFF (ROM) $8000-$FFFF (ROM)

RAM is always mapped at $6000-$7FFF, and the bit $5113.7 is ignored. ROM is always mapped at the bank controlled by register $5117, and the bit $5117.7 is ignored. This makes it impossible to map RAM at interrupt vectors in any mode.

Modes 0-2 : The bankswitching registers always hold a value of 8kb bank index numbers. When selecting banks of a "larger" size (16 kb or 32kb), the low bits in the bankswitching register are ignored. In other words, the address lines from the CPU are passed through the mapper directly to the PRG-ROM chip.

Games seem to expect $5117 to be $FF at power on. All games have their reset vector in the last bank of PRG ROM, and the vector points to an address greater than or equal to $E000.

PRG-RAM bankswitching quirks

Until November 2018, it was thought that the MMC5 supported up to 2 PRG RAM chips, each up to 32KB in length. However, research in 2018 found that two previously-unknown pins act like PRG RAM A15 and A16, allowing up to 128KB RAM support. Either or both chips may be battery-backed; 11 of the 15 MMC5 games include a battery. The following configurations of PRG-RAM are known to exist in ExROM games:

  • 0KB: No PRG-RAM
  • 8KB: 1x 8KB chip
  • 16KB: 2x 8KB chips
  • 32KB: 1x 32KB chip

In the original .NES format, byte 8 of the file's header should indicate how many pages are present, but ROM images in the wild that use this mapper may not have byte 8 set correctly, nor do emulators necessarily honor this number. Byte 10 of the NES 2.0 header should be reliable.

Emulation quirks with commercial games

  • Bandit Kings of Ancient China maps PRG-RAM to the CPU $8000+ area and expects to be able to write to it through there. Failure to emulate this causes corruption when the background is restored on the world map.
  • Uncharted Waters requires emulating bankswitching of PRG RAM: it writes to PRG RAM at one CPU address and expects to be able to read the same data back via a different CPU address.
  • No ExROM game is known to write PRG RAM with one bank value and then attempt to read back the same data with a mirror of different bank value. So lacking better information, mirroring can be ignored, 64KB of WRAM could be emulated at all times, and $5113 can be treated as a simple page offset into that 64KB. Emulating 32KB won't work, even if no games used more than that; because 16KB games will expect to see their two distinct pages by toggling bit 2, not bit 0. However, it's not advisable to rely on this fallback behavior for newly produced homebrew because people making a physical reproduction will not know from the header how much RAM to include on the cartridge board.[2]

CHR Bankswitching ($5120-$5130)

When using 8x8 sprites, only registers $5120-$5127 are used. Registers $5128-$512B are completely ignored.

When using 8x16 sprites, registers $5120-$5127 specify banks for sprites, registers $5128-$512B apply to background tiles, and the last set of registers written to (either $5120-$5127 or $5128-$512B) will be used for I/O via PPUDATA ($2007). [1] [2] The MMC5 knows that sprite data is being fetched by counting the number of fetches since the last detected scanline start, similar to how it detects the position for the vertical split.

Bandit Kings of Ancient China and Uchuu Keibitai SDF have non-pattern data stored in CHR ROM, read out via $2007.

The MMC5 is known to listen to the same address as the PPU to find out when to enable the 8x16 sprite mode; see above.

CHR select $5120-$512B

PPU memory affected for each mode (see #CHR mode ($5101))
Register 1 KiB 2 KiB 4 KiB 8 KiB
$5120 $0000-$03FF none none none
$5121 $0400-$07FF $0000-$07FF none none
$5122 $0800-$0BFF none none none
$5123 $0C00-$0FFF $0800-$0FFF $0000-$0FFF none
$5124 $1000-$13FF none none none
$5125 $1400-$17FF $1000-$17FF none none
$5126 $1800-$1BFF none none none
$5127 $1C00-$1FFF $1800-$1FFF $1000-$1FFF $0000-$1FFF
$5128 $0000-$03FF and $1000-$13FF none none none
$5129 $0400-$07FF and $1400-$17FF $0000-$07FF and $1000-$17FF none none
$512A $0800-$0BFF and $1800-$1BFF none none none
$512B $0C00-$0FFF and $1C00-$1FFF $0800-$0FFF and $1800-$1FFF $0000-$0FFF and $1000-$1FFF $0000-$1FFF

Caution: Unlike the MMC1 and unlike PRG banking on the MMC5, the banks are always indexed by the currently selected size. When using 2kb, 4kb or 8kb bank sizes, the registers hold bank index of that larger size, and lower bits are *not* ignored.

Upper CHR Bank bits ($5130)

7  bit  0
---- ----
xxxx xxBB
       ||
       ++- Upper bits for subsequent CHR bank writes

When the MMC5 is using 2KB/1KB CHR banks, only 512KB/256KB of CHR ROM can be selected using the previous registers. To access all 1024KB in those modes, first write the upper bit(s) to register $5130 and then write the lower bits to $5120-$512B. When the Extended RAM mode is set to 1, this selects which 256KB of CHR ROM is to be used for all background tiles on the screen.

The only ExROM game with CHR ROM larger than 256KB is Metal Slader Glory, which uses 4KB CHR banks and does not use extended attributes. In other words, no official game relies on this register, and most don't even initialize it.

Other Registers

Vertical Split Mode ($5200)

7  bit  0
---- ----
ESxW WWWW
|| | ||||
|| +-++++- Specify vertical split start/stop tile
|+-------- Specify vertical split screen side (0:left; 1:right)
+--------- Enable vertical split mode

When vertical split mode is enabled, all VRAM fetches corresponding to the appropriate screen region will be redirected to Extended RAM (as long as its mode is set to 0 or 1).

Uchuu Keibitai SDF uses split screen mode during the intro, where it shows ship stats. Bandit Kings of Ancient China uses split screen mode during the ending sequence[3].

Operation Notes

34 BG tiles are fetched per scanline. MMC5 performs the split by watching which BG tile is being fetched, and if it is within the split region, replacing the normal NT data with the split screen data according to the absolute screen position of the tile (i.e., ignoring the coarse horizontal and vertical scroll output as part of the VRAM address for the fetch). Since it operates on a per-tile basis, fine horizontal scrolling "carries into" the split region: setting the horizontal scroll to 1-7 will result in the split being moved to the left 1-7 pixels. Whenever scrolling exceeds a multiple of 8, the split will "snap" back to its normal position.

Left Split:

  • Tiles 0 to T-1 are the split.
  • Tiles T and on are rendered normally.

Right Split:

  • Tiles 0 to T-1 are rendered normally.
  • Tiles T and on are the split.

There is no coarse horizontal scrolling of any kind for the split. Right-side splits will always show the right-hand side of the nametable, and left-hand splits will always show the left-hand side of the nametable. Coarse horizontal scrolling can still be used for the non-split region.

ExRAM is always used as the nametable in split screen mode.

Vertical scrolling for the split operates like normal vertical scrolling. 0-239 are valid scroll values, whereas 240-255 will display Attribute table data as NT data for the first few scanlines. The split nametable will wrap so that the top of the nametable will appear below as you scroll (just as if vertical mirroring were employed).

$5202 selects (yet another) CHR page to use for the BG. This page is used for the split region only.

Vertical Split Scroll ($5201)

 All eight bits specify the vertical scroll value to use in split region

MMC5 boards wired in "CL" mode should only use vertical scroll values whose bottom 3 bits match the PPU's fine vertical scroll value. Using a mismatched value will cause tiles to seem to "roll" within themselves. In "SL" mode, any values can be used.

Horizontal scrolling is not allowed within the split region.

Vertical Split Bank ($5202)

 All eight bits select a 4 KB CHR bank at $0000-$0FFF and $1000-$1FFF while rendering the split region.

Scanline Number IRQ ($5203)

 All eight bits specify the scanline number at which to generate a scanline IRQ.  Value $00 is a special case that does not generate IRQ.

Scanline IRQ Status ($5204, read/write)

Write
7  bit  0
---- ----
Exxx xxxx
|
+--------- Scanline IRQ Enable flag (1=enabled)
Read
7  bit  0
---- ----
SVxx xxxx  MMC5A default power-on value = $00
||
|+-------- "In Frame" flag
+--------- Scanline IRQ Pending flag

The Scanline IRQ Pending flag becomes set at any time that the internal scanline counter matches the value written to register $5203. If the scanline IRQ is enabled, it will also generate /IRQ to the system.

The "In Frame" flag is set when the PPU is rendering a frame and cleared during vertical blank.

Any time this register is read, the Scanline IRQ Pending flag is cleared (acknowledging the IRQ).

For details, see IRQ counter operation.

Unsigned 8x8 to 16 Multiplier ($5205, $5206 read/write)

The unsigned 16-bit product is available to be read from these registers immediately after writing. All 65536 combinations of multiplicand and multiplier were tested and verified correct on MMC5A here[3].

Write
  • $5205 8-bit Unsigned Multiplicand
  • $5206 8-bit Unsigned Multiplier
  • MMC5A default power-on write value = $FF for both of these registers.
Read
  • $5205 Unsigned 16-bit Product (low byte)
  • $5206 Unsigned 16-bit Product (high byte)
  • MMC5A default power-on read value = $FE01, i.e. $FF * $FF.

MMC5A Only

Registers $5207, $5208, $5209, $520A, and range $5800-$5BFF are present only in MMC5A.

CL3 / SL3 Data Direction and Output Data Source (MMC5A: $5207 write only)

7  bit  0
---- ----
ABxx xxCD  MMC5A default power-on write value = 11xx xxxx
||     ||
||     |+- MMC5.97 (CL3) Output Data Source (0 = $5208.6 value written, 1 = !(M2) when CPU is reading in range $5800-$5BFF)
||     +-- MMC5.98 (SL3) Output Data Source (0 = $5208.7 value written, 1 = !(M2) when CPU is writing in range $5800-$5BFF)
|+-------- MMC5.97 (CL3) Data Direction (0 = output, 1 = input)
+--------- MMC5.98 (SL3) Data Direction (0 = output, 1 = input)

CL3 / SL3 Status (MMC5A: $5208 read/write)

Write
7  bit  0
---- ----
ABxx xxxx  MMC5A default power-on write value = 00xx xxxx
||
|+-------- Value to be output on MMC5.97 pin (CL3) if/when $5207.0 = 0 and $5207.6 = 0
+--------- Value to be output on MMC5.98 pin (SL3) if/when $5207.1 = 0 and $5207.7 = 0
Read
7  bit  0
---- ----
ABxx xxxx
||
|+-------- Input value of MMC5.97 pin (CL3)
+--------- Input value of MMC5.98 pin (SL3)

16-bit Hardware Timer with IRQ (MMC5A: $5209 read/write, $520A write)

Read
  • $5209
7  bit  0
---- ----
Vxxx xxxx  MMC5A default power-on read value = $00
|
+--------- Hardware Timer IRQ Flag
Write
  • $5209
7  bit  0
---- ----
TTTT TTTT  MMC5A default power-on write value = $00
|||| ||||
++++-++++- Timer count LSB
  • $520A
7  bit  0
---- ----
TTTT TTTT  MMC5A default power-on write value = $00
|||| ||||
++++-++++- Timer count MSB

Based on findings from krzysiobal: The timer automatically starts when writing any value to register $5209, if the 16-bit timer value does not equal $0000. For example, to write value $0100, you would first write $01 (MSB) to register $520A, which does not start the timer. Then write $00 (LSB) to register $5209, which at that point will start the timer from value $0100.

Each 8-bit value is written directly to an internal 16-bit counter that decrements on each rising edge of M2. Additional writes while the timer is running will directly overwrite that portion of the counter. Reading register $5209 while the timer is running reports $00. The transition from counter value $0001 to $0000 generates an IRQ and sets the hardware timer IRQ flag. The timer stops at this point. Reading this register reports the IRQ flag, then automatically clears the IRQ and IRQ flag.

If the MMC5 detects a reset, it clears the timer if active, and it clears the IRQ and IRQ flag if set. Reset detection works by looking for a gap larger than about 11 usec on M2.

This register's IRQ operation is completely independent from register $5204. Disabling interrupts through $5204 does not make any effect, also reading $5204 does not report IRQ pending when IRQ is asserted by $5209.

Unknown Address Range (MMC5A: $5800-$5BFF, write only)

Reads and writes in this address range are reflected on the CL3 and SL3 pins when register $5207 = $03. The purpose of this function is unknown. Minute VCC current spikes shortly after rising edge of M2 during writes in this range exhibit the same characteristics as writes in expansion RAM range $5C00-$5FFF, suggesting possible existence of RAM in this range, though experimentally reading from this range is always met with open CPU bus.

Address $5800 is written to by Just Breed. During each V-Blank, it writes value $03, then $01 to this address, reads and writes to PPU registers, then writes value $00 to this address once complete.

Expansion RAM ($5C00-$5FFF, read/write)

  • Mode 0/1 - Not readable (returns open bus), can only be written while the PPU is rendering (otherwise, 0 is written)
  • Mode 2 - Readable and writable
  • Mode 3 - Read-only

In Mode 1, nametable fetches are processed normally, and can come from CIRAM nametables, fill mode, or even Expansion RAM, but attribute fetches are replaced by data from Expansion RAM.

Each byte of Expansion RAM is used to enhance the tile at the corresponding address in every nametable (so the extended attributes are 1-screen mirrored):

7  bit  0
---- ----
AACC CCCC
|||| ||||
||++-++++- Select 4 KB CHR bank to use with specified tile
++-------- Select palette to use with specified tile

The pattern fetches ignore the standard CHR banking bits, and instead use the top two bits of $5130 and the bottom 6 bits from Expansion RAM to choose a 4KB bank to select the tile from.

Just Breed, Yakuman Tengoku, and the Koei games use extended attributes continuously.

Scanline Detection and Scanline IRQ

MMC5 'in frame' status bit state diagram

The MMC5 detects scanlines by first looking for three consecutive PPU reads from the same nametable address in the range $2xxx. Once this has been seen, the next PPU read, regardless of address, is the point at which the scanline is detected. This works because the PPU does two matching dummy nametable byte reads at the end of each scanline, followed by a third matching nametable byte read at the beginning of the next scanline, followed by an attribute table byte read. So, the scanline gets detected when the PPU does the attribute table byte read, which is at PPU cycle 4.

Once that occurs, if the "in-frame" flag (register $5204) was clear, it becomes set, and the internal 8-bit scanline counter is reset to zero; but if it was already set, the scanline counter is incremented, then compared against the value written to $5203. If they match, the "irq pending" flag is set.

The IRQ pending flag is raised when the desired scanline is reached regardless of whether or not the scanline IRQ is enabled, i.e. even after a 0 was written to the scanline IRQ enable flag. However, an actual IRQ is only sent to the CPU if both the scanline IRQ enable flag and IRQ pending flag are set. A $5203 value of $00 is a special case that will never generate an IRQ. The MMC5's scanline IRQ occurs at PPU cycle 4, unlike the simpler scanline counter of the MMC3, which usually generates an IRQ around PPU cycle 260. See also [4].

The "in-frame" flag is cleared when the PPU is no longer rendering. This is detected when 3 CPU cycles pass without a PPU read having occurred (PPU /RD has not been low during the last 3 M2 rises). The PPU does this in these conditions:

  • the PPU begins the post-render scanline 240
  • the PPU stops rendering because the user program wrote to CPU address $2001 with bits 3 and 4 clear.
  • note: the MMC5 does not listen directly to writes to $2001 for this behavior.

The "in frame" flag is cleared, scanline IRQ is automatically acknowledged, and the internal scanline counter is reset in any of these conditions:

  • the V-blank NMI occurs, i.e. CPU reads the interrupt vector from addresses $FFFA and $FFFB
  • the user program intentionally reads from CPU addresses $FFFA or $FFFB
  • the 241st scanline is detected.

The scanline IRQ is acknowledged, but the "in frame" flag is not cleared and the scanline counter is not reset in any of these conditions:

  • the user program reads register $5204
  • scanline 0 is detected

When system reset detection occurs, the only thing that happens is scanline IRQ becomes disabled. All other operation continues unaffected. These things happen any time that scanline IRQ becomes disabled:

  • if /IRQ was low due to scanline IRQ pending flag, /IRQ returns high
  • the scanline IRQ pending flag remains unaffected
  • register $5203 value remains unaffected
  • scanline counter remains unaffected
  • enabling the scanline IRQ will cause immediate /IRQ low if IRQ pending flag is set, but will not affect anything else

This means in pseudo-code:

(On every PPU read -- PPU /RD falling edge)
if address >= $2000 and address <= $2FFF and address == lastAddress
   matchCount := matchCount +1
   if matchCount == 2
     if inFrame == false
        inFrame := true
        scanline := 0
     else
        scanline := scanline +1
        if scanline == [$5203]
           irqPending := true
else
   matchCount := 0
lastAddress := address
ppuIsReading := true

(On every CPU cycle -- M2 rising edge)
if ppuIsReading
   idleCount := 0
else
   idleCount := idleCount +1      
   if idleCount == 3
      inFrame := false
      lastAddress := undefined
ppuIsReading := false

(On every CPU write)
if address == $2001 and (value & $18) == 0
   inFrame := false
   lastAddress := undefined

(On every CPU read)
if address == $FFFA or address == $FFFB
   inFrame := false
   lastAddress := undefined

Please refer to the state diagrams on the right for a more formal description of the scanline and in-frame detection counters.

The system reset detection observed in the 16-bit software timer does not appear to have any effect on the 'in frame' status bit or the state diagram on the right. It is unknown if reset detection clears the scanline counter or a pending scanline IRQ.

Hardware

The MMC5 exists in a 100-pin rectangular QFP package, see MMC5 pinout for details.

MMC5 cartridge PCBs can be configured to different modes, see ExROM for details.

At least two different versions of the MMC5 are known to exist: MMC5, and MMC5A. MMC5A has the addition of registers $5207, $5208, $5209, and $520A: SL3/CL3 control and hardware timer.

References

  1. krzysiobal's RE notes
  2. lidnariq's comment about puNES
  3. https://forums.nesdev.com/viewtopic.php?f=2&t=12764

External links

  • NES Mapper list by Disch [5]
  • Nintendo MMC5 by goroh, translated by Sgt. Bowhack [6]
  • Nintendo MMC5 Bankswitching by Kevin Horton [7]