Difference between revisions of "INES Mapper 206"

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(Thanks to lupin3rd, we can remove my doublespeak.)
m (References: Link to the FCEUX source code (map206))
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== References ==
== References ==
*FCEUX source code
*[https://github.com/asfdfdfd/fceux/blob/master/src/boards/206.cpp FCEUX source code]
*[http://www43.tok2.com/home/cmpslv/ Enri]'s reverse-engineered schematic of PCBs 3407 and 3416: http://www43.tok2.com/home/cmpslv/Famic/Fcmp206.htm
*[http://www43.tok2.com/home/cmpslv/ Enri]'s reverse-engineered schematic of PCBs 3407 and 3416: http://www43.tok2.com/home/cmpslv/Famic/Fcmp206.htm
*[http://forums.nesdev.com/viewtopic.php?t=13297 Naruko's forum thread] about mapper register range
*[http://forums.nesdev.com/viewtopic.php?t=13297 Naruko's forum thread] about mapper register range

Revision as of 17:57, 21 February 2017

Namco 118, Tengen MIMIC-1
Company Namco, Tengen, others
Games 39 in NesCartDB
Complexity ASIC
Boards 34xx, DxROM
PRG ROM capacity 128K
PRG ROM window 8K + 8K + 16K fixed
PRG RAM capacity None
CHR capacity 64K
CHR window 2Kx2 + 1Kx4
Nametable mirroring Fixed H/V, or 4
Bus conflicts No
Audio No
iNES mappers 206, 76, 88, 154, 95
iNES Mapper 206 is the simpler predecessor of the MMC3, and was used by Tengen and Namco.

Chips used include "Tengen MIMIC-1" and "Namcot 118", and the boards made by Nintendo of America that used this mapper are NES-DxROM. Many ROMS using this mapper are incorrectly listed as using MMC3, but will usually work if emulated with MMC3, and the mirroring is correct, as if they were on a TEROM or TFROM board.

Compared to MMC3:

  • There are no IRQs
  • There is no WRAM support
  • PRG always has the last two 8KiB banks fixed to the end.
  • CHR always gives the left pattern table (0000-0FFF) the two 2KiB banks, and the right pattern table (1000-1FFF) the four 1KiB banks.
  • Mirroring is hardwired, one game uses 4-screen mirroring (Gauntlet, DRROM).
  • CHR size limit is 64KiB, PRG size limit is 128KiB.
  • There are no control registers in the $A000-$FFFF range.
    • Naruko observed a bug where writes to RAM (i.e. $0000-$1FFF) while executing code from $8000-$9FFF will cause erratic mapper writes. It is not known whether all five ICs (108, 109, 118, 119, MIMIC-1) have this same bug.

Register mask: $E001

  • $8000: 00000xxx - Select which internal register gets written by $8001
  • $8001: 00xxxxxx - Value written to the internal register. PRG registers use only 4 bits.

Internal registers:

  • 0, 1: 2k CHR banks at 0000, 0800. Least significant bit is ignored.
  • 2, 3, 4, 5: 1k CHR banks at 1000, 1400, 1800, 1C00.
  • 6, 7: 8k PRG banks at 8000, A000.


The game Babel no Tou, on the PCB 3401, is the only game with 32 KiB PRG that allows—and uses!—PRG banking. All other games with 32 KiB PRG connect CPU A13 and CPU A14 directly to the PRG ROM, but fortunately they initialize their PRG registers to work on a normal board. Because all six games can be correctly emulated by respecting the PRG banking registers, it seems no submapper needs to be allocated for this variation.


Mapper 76 increases CHR to 128KiB by inflating the 1KiB CHR banks to 2KiB and making the originally-2KiB banks inaccessible.

Mapper 88 increases CHR to 128KiB by connecting PPU's A12 line to the CHR ROM's A16 line, making tiles in $0000 and $1000 come from disjoint sections of ROM. Because an undersize ROM on a mapper 88 board behaves identically to mapper 206, emulators may treat these mapper numbers as synonymous.

Mapper 154 has the same as mapper 88, plus mapper-controlled one-screen mirroring.

Mapper 95 uses the MSB to control mirroring by connecting CHR A15 to CIRAM A10, much as CHR A17 controls CIRAM A10 in TxSROM.