Difference between revisions of "MMC2"

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(Banks: clarifying why it matters that sprites use $0000 and background uses $1000)
(moving the CHR banking stuff to its own section)
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* PPU $1000-$1FFF: Two 4 KB switchable CHR ROM banks
 
* PPU $1000-$1FFF: Two 4 KB switchable CHR ROM banks
  
When the PPU reads from specific tiles ($FD or $FE) in the pattern table during rendering, the MMC2 sets a latch that tells it to use a different 4 KB bank number. On the background layer, this has the effect of setting a different bank for all tiles to the right of a given tile, virtually increasing the tile count limit from 256 to 512 without monopolizing the CPU.
+
The two 4 KB PPU banks each have two 4 KB banks, which can be switched during rendering by using the special tiles $FD or $FE in either a sprite or the background. See [[#CHR banking|CHR banking]] below.
 
+
*PPU reads $0FD8: latch 0 is set to $FD for subsequent reads
+
*PPU reads $0FE8: latch 0 is set to $FE for subsequent reads
+
*PPU reads $1FD8 through $1FDF: latch 1 is set to $FD for subsequent reads
+
*PPU reads $1FE8 through $1FEF: latch 1 is set to $FE for subsequent reads
+
 
+
Notice that latch 0 only responds to one address, but latch 1 responds to a range of addresses. This means that:
+
* The left ($0000-0FFF) pattern table only switches on the ''top row'' of the 8x8 tile
+
* The right ($1000-1FFF) pattern table switches on ''every row'' of the 8x8 tile
+
 
+
Because latch 1 is expected to use the background nametable, the same tiles are going to be fetched for 8 scanlines, so extra circuitry to select only the first row was unnecessary. Latch 0 is intended for sprites, which allows more arbitrary arrangement, hence it is designed to operate only on the first row of the tile.
+
 
+
Note that the latch is updated ''after'' either pattern table byte is fetched, so the tiles $FD and $FE are drawn using the old CHR-bank before the new latch value is set.
+
 
+
Also since the PPU fetches 34 background tiles per scanline (and at most 33 are drawn), it is possible to rely on fetches of tiles that won't show up on the screen to set latches to a known value on the next scanline. If vertical [[mirroring]] is used, these switch tiles can therefore be completely invisible.
+
  
 
== Registers ==
 
== Registers ==
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         |
 
         |
 
         +- Select nametable mirroring (0: vertical; 1: horizontal)
 
         +- Select nametable mirroring (0: vertical; 1: horizontal)
 +
 +
== CHR banking ==
 +
 +
When the PPU reads from specific tiles ($FD or $FE) in the pattern table during rendering, the MMC2 sets a latch that tells it to use a different 4 KB bank number. On the background layer, this has the effect of setting a different bank for all tiles to the right of a given tile, virtually increasing the tile count limit from 256 to 512 without monopolizing the CPU.
 +
 +
*PPU reads $0FD8: latch 0 is set to $FD for subsequent reads
 +
*PPU reads $0FE8: latch 0 is set to $FE for subsequent reads
 +
*PPU reads $1FD8 through $1FDF: latch 1 is set to $FD for subsequent reads
 +
*PPU reads $1FE8 through $1FEF: latch 1 is set to $FE for subsequent reads
 +
 +
Notice that latch 0 only responds to one address, but latch 1 responds to a range of addresses. This means that:
 +
* The left ($0000-0FFF) pattern table only switches on the ''top row'' of the 8x8 tile
 +
* The right ($1000-1FFF) pattern table switches on ''every row'' of the 8x8 tile
 +
 +
Because latch 1 is expected to use the background nametable, the same tiles are going to be fetched for 8 scanlines, so extra circuitry to select only the first row was unnecessary. Latch 0 is intended for sprites, which allows more arbitrary arrangement, hence it is designed to operate only on the first row of the tile.
 +
 +
Note that the latch is updated ''after'' either pattern table byte is fetched, so the tiles $FD and $FE are drawn using the old CHR-bank before the new latch value is set.
 +
 +
An additional trick is possible with the background: since the PPU fetches 34 background tiles per scanline (and at most 33 are drawn), you can use vertical [[mirroring]] to place a switching tile just past the edge of the screen, where it will be unseen.
  
 
== Hardware ==
 
== Hardware ==

Revision as of 18:23, 30 May 2015


MMC2
PxROM
Company Nintendo
Games 1 in NesCartDB
Complexity ASIC
Boards PNROM, PEEOROM
PRG ROM capacity 128K
PRG ROM window 8K + 24K fixed
PRG RAM capacity 8K (PC10 ver.)
PRG RAM window Fixed
CHR capacity 128K
CHR window 4K + 4K (triggered)
Nametable mirroring H or V, switchable
Bus conflicts No
IRQ No
Audio No
iNES mappers 009

The Nintendo MMC2 is an ASIC mapper, used on the PNROM and PEEOROM Nintendo Game Pak boards for Mike Tyson's Punch Out!!. The iNES format assigns Mapper 009 to PxROM. This chip appeared in November 1987.

Banks

  • CPU $6000-$7FFF: 8 KB PRG RAM bank (PlayChoice version only; contains a 6264 and 74139)
  • CPU $8000-$9FFF: 8 KB switchable PRG ROM bank
  • CPU $A000-$FFFF: Three 8 KB PRG ROM banks, fixed to the last three banks
  • PPU $0000-$0FFF: Two 4 KB switchable CHR ROM banks
  • PPU $1000-$1FFF: Two 4 KB switchable CHR ROM banks

The two 4 KB PPU banks each have two 4 KB banks, which can be switched during rendering by using the special tiles $FD or $FE in either a sprite or the background. See CHR banking below.

Registers

PRG ROM bank select ($A000-$AFFF)

7  bit  0
---- ----
xxxx PPPP
     ||||
     ++++- Select 8 KB PRG ROM bank for CPU $8000-$9FFF

CHR ROM $FD/0000 bank select ($B000-$BFFF)

7  bit  0
---- ----
xxxC CCCC
   | ||||
   +-++++- Select 4 KB CHR ROM bank for PPU $0000-$0FFF
           used when latch 0 = $FD

CHR ROM $FE/0000 bank select ($C000-$CFFF)

7  bit  0
---- ----
xxxC CCCC
   | ||||
   +-++++- Select 4 KB CHR ROM bank for PPU $0000-$0FFF
           used when latch 0 = $FE

CHR ROM $FD/1000 bank select ($D000-$DFFF)

7  bit  0
---- ----
xxxC CCCC
   | ||||
   +-++++- Select 4 KB CHR ROM bank for PPU $1000-$1FFF
           used when latch 1 = $FD

CHR ROM $FE/1000 bank select ($E000-$EFFF)

7  bit  0
---- ----
xxxC CCCC
   | ||||
   +-++++- Select 4 KB CHR ROM bank for PPU $1000-$1FFF
           used when latch 1 = $FE

Mirroring ($F000-$FFFF)

7  bit  0
---- ----
xxxx xxxM
        |
        +- Select nametable mirroring (0: vertical; 1: horizontal)

CHR banking

When the PPU reads from specific tiles ($FD or $FE) in the pattern table during rendering, the MMC2 sets a latch that tells it to use a different 4 KB bank number. On the background layer, this has the effect of setting a different bank for all tiles to the right of a given tile, virtually increasing the tile count limit from 256 to 512 without monopolizing the CPU.

  • PPU reads $0FD8: latch 0 is set to $FD for subsequent reads
  • PPU reads $0FE8: latch 0 is set to $FE for subsequent reads
  • PPU reads $1FD8 through $1FDF: latch 1 is set to $FD for subsequent reads
  • PPU reads $1FE8 through $1FEF: latch 1 is set to $FE for subsequent reads

Notice that latch 0 only responds to one address, but latch 1 responds to a range of addresses. This means that:

  • The left ($0000-0FFF) pattern table only switches on the top row of the 8x8 tile
  • The right ($1000-1FFF) pattern table switches on every row of the 8x8 tile

Because latch 1 is expected to use the background nametable, the same tiles are going to be fetched for 8 scanlines, so extra circuitry to select only the first row was unnecessary. Latch 0 is intended for sprites, which allows more arbitrary arrangement, hence it is designed to operate only on the first row of the tile.

Note that the latch is updated after either pattern table byte is fetched, so the tiles $FD and $FE are drawn using the old CHR-bank before the new latch value is set.

An additional trick is possible with the background: since the PPU fetches 34 background tiles per scanline (and at most 33 are drawn), you can use vertical mirroring to place a switching tile just past the edge of the screen, where it will be unseen.

Hardware

The MMC2 is implemented in a 40-pin shrink-DIP package. At least two revisions are known to exist, the MMC2 and the MMC2-L.

The PEEOROM board is used in the re-issue of Mike Tyson's Punch-Out!!. Unlike PNROM, and unlike most other boards used in NES Game Paks sold to the public, it can be configured to support EPROM memory through jumpers on the board.

A pirate clone that exclusively uses discrete logic has been found and reverse-engineered. [1]

Variants

Nintendo's MMC4, used in the FxROM board set, is a similar mapper with PRG RAM support and PRG bank sizes of 16kb instead of 8kb. It also suppresses the different banking behavior of the left pattern table.

Because of the extreme similarity between both chips (MMC2 and MMC4), it is possible to make a circuit that simulates a MMC4 from a MMC2, although, it is doubtful whether Nintendo ever exploited this publicly.

For example, with the help of a 7402 quad-NOR gate and a 7420 4-input NAND gate to decode PRG RAM, one can make the MMC2 act like an MMC4. The following circuit "tricks" the MMC2 into thinking the program is still in the $8000-$9fff range when reading from $A000-$BFFF, but doesn't affect mapper writes. It also shifts all addresses left one bit so that it switches 16kB instead of 8kB banks, and it shortcuts around the different behavior for pattern tables at $0000 and $1000.

MMC2 A16  ----------------------------------  PRG A17

MMC2 A15  ----------------------------------  PRG A16

MMC2 A14  ----------------------------------  PRG A15
                ____              ___
MMC2 A13  -----\    `.       ,---\   `.
                )     )o-----+    )    )o---  PRG A14
CPU A14   -----/____,'       `---/___,'  

CPU A13   ---+------------------------------  PRG A13
             |    ___
             +---\   `.         ___
             |    )    )o------\   `.
             `---/___,'         )    )o-----  MMC2 A13
                          ,----/___,'
R/W       ----------------'

GND       --------------------+-------------  MMC2 PA2
                              |
                              +-------------  MMC2 PA1
                              |
                              `-------------  MMC2 PA0

See also