Difference between revisions of "PPU memory map"

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m (First draft of PPU memory adress. Must be improved)
 
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=== RAM memory map ===
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=== PPU memory map ===
  
{| border=1
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The [[PPU]] addresses a 16kB space, $0000-3FFF, completely separate from the CPU's address bus. It is either directly accessed by the PPU itself, or via the CPU with [[PPU registers|memory mapped registers]] at $2006 and $2007.
! Address || Size || Description
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|-
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| $0000 || $1000 || Pattern Table #0
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|-
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| $1000 || $1000 || Pattern Table #1
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|-
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| $2000  ||$0800 || Name Tables
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|-
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| $2000  ||$0020 || Palettes
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|}
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The NES has 2kB of RAM dedicated to the PPU, normally mapped to the nametable address space from $2000-2FFF, but this can be rerouted through custom cartridge wiring.
  
=== Programmer memory map ===
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{| class="tabular"
{| border=1
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! Address range || Size || Description
! Address || Size || Flags || Description
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|-
 
|-
| $0000 || $1000 || C---- || Pattern Table #0
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| $0000-$0FFF || $1000 || [[PPU pattern tables|Pattern table]] 0
 
|-
 
|-
| $1000 || $1000 || C---- || Pattern Table #1
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| $1000-$1FFF || $1000 || Pattern table 1
 
|-
 
|-
| $2000  ||$03C0 || ----- || Name Table #0
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| $2000-$23FF || $0400 || [[PPU nametables|Nametable]] 0
 
|-
 
|-
| $23C0 ||$0040 || -N--- || Attribute Table #0
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| $2400-$27FF || $0400 || Nametable 1
 
|-
 
|-
| $2400 ||$03C0 || -N--- || Name Table #1
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| $2800-$2BFF || $0400 || Nametable 2
 
|-
 
|-
| $27C0 ||$0040 || -N--- || Attribute Table #1
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| $2C00-$2FFF || $0400 || Nametable 3
 
|-
 
|-
| $2800 ||$03C0 || -N--- || Name Table #2
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| $3000-$3EFF || $0F00 || Mirrors of $2000-$2EFF
 
|-
 
|-
| $2BC0 ||$0040 || -N--- || Attribute Table #2
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| $3F00-$3F1F || $0020 || [[PPU palettes|Palette RAM]] indexes
 
|-
 
|-
| $2C00 ||$03C0 || -N--- || Name Table #3
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| $3F20-$3FFF || $00E0 || Mirrors of $3F00-$3F1F
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|}
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In addition, the PPU internally contains 256 bytes of memory known as [[PPU OAM|Object Attribute Memory]] which determines how sprites are rendered. The CPU can manipulate this memory through [[PPU registers|memory mapped registers]] at [[OAMADDR]] ($2003), [[OAMDATA]] ($2004), and [[OAMDMA]] ($4014). OAM can be viewed as an array with 64 entries. Each entry has 4 bytes: the sprite Y coordinate, the sprite tile number, the sprite attribute, and the sprite X coordinate.
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{| class="tabular"
 +
! Address Low Nibble || Description
 
|-
 
|-
| $2FC0  ||$0040 || -N--- || Attribute Table #3
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| $00, $04, $08, $0C || Sprite Y coordinate
 
|-
 
|-
| $3000  ||$0F00 || --R-- ||  
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| $01, $05, $09, $0D || Sprite tile #
 
|-
 
|-
| $3F00  ||$0010 || ----- || Image palette #1
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| $02, $06, $0A, $0E || Sprite attribute
 
|-
 
|-
| $3F10  ||$0010 || ----- || Sprite palette #1
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| $03, $07, $0B, $0F || Sprite X coordinate
|-
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| $3F20  ||$00E0 || ---P- ||
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|-
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| $4000  ||$C000 || ---P- ||  
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|}
 
|}
  
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== Hardware mapping ==
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 +
The mappings above are the fixed addresses from which the PPU uses to fetch data during rendering. The actual device that the PPU fetches data from, however, may be configured by the cartridge.
 +
 +
* $0000-1FFF is normally mapped by the cartridge to a [[CHR ROM vs. CHR RAM|CHR-ROM or CHR-RAM]], often with a bank switching mechanism.
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 +
* $2000-2FFF is normally mapped to the 2kB NES internal VRAM, providing 2 nametables with a [[Mirroring#Nametable_Mirroring|mirroring]] configuration controlled by the cartridge, but it can be partly or fully remapped to RAM on the cartridge, allowing up to 4 simultaneous nametables.
  
* C = Possibly CHR-ROM
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* $3000-3EFF is usually a mirror of the 2kB region from $2000-2EFF. The PPU does not render from this address range, so this space has negligible utility.
* N = Mirrored (see Subsection ??)
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* P = Mirrored (see Subsection ??)
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* R = Mirror of $2000-2EFF (VRAM)
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* F = Mirror of $0000-3FFF (VRAM)
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----
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* $3F00-3FFF is not configurable, always mapped to the internal palette control.
Note: First draft of the PPU memory map. Taken nesdoc format as example
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Latest revision as of 17:41, 17 March 2019

PPU memory map

The PPU addresses a 16kB space, $0000-3FFF, completely separate from the CPU's address bus. It is either directly accessed by the PPU itself, or via the CPU with memory mapped registers at $2006 and $2007.

The NES has 2kB of RAM dedicated to the PPU, normally mapped to the nametable address space from $2000-2FFF, but this can be rerouted through custom cartridge wiring.

Address range Size Description
$0000-$0FFF $1000 Pattern table 0
$1000-$1FFF $1000 Pattern table 1
$2000-$23FF $0400 Nametable 0
$2400-$27FF $0400 Nametable 1
$2800-$2BFF $0400 Nametable 2
$2C00-$2FFF $0400 Nametable 3
$3000-$3EFF $0F00 Mirrors of $2000-$2EFF
$3F00-$3F1F $0020 Palette RAM indexes
$3F20-$3FFF $00E0 Mirrors of $3F00-$3F1F

In addition, the PPU internally contains 256 bytes of memory known as Object Attribute Memory which determines how sprites are rendered. The CPU can manipulate this memory through memory mapped registers at OAMADDR ($2003), OAMDATA ($2004), and OAMDMA ($4014). OAM can be viewed as an array with 64 entries. Each entry has 4 bytes: the sprite Y coordinate, the sprite tile number, the sprite attribute, and the sprite X coordinate.

Address Low Nibble Description
$00, $04, $08, $0C Sprite Y coordinate
$01, $05, $09, $0D Sprite tile #
$02, $06, $0A, $0E Sprite attribute
$03, $07, $0B, $0F Sprite X coordinate

Hardware mapping

The mappings above are the fixed addresses from which the PPU uses to fetch data during rendering. The actual device that the PPU fetches data from, however, may be configured by the cartridge.

  • $0000-1FFF is normally mapped by the cartridge to a CHR-ROM or CHR-RAM, often with a bank switching mechanism.
  • $2000-2FFF is normally mapped to the 2kB NES internal VRAM, providing 2 nametables with a mirroring configuration controlled by the cartridge, but it can be partly or fully remapped to RAM on the cartridge, allowing up to 4 simultaneous nametables.
  • $3000-3EFF is usually a mirror of the 2kB region from $2000-2EFF. The PPU does not render from this address range, so this space has negligible utility.
  • $3F00-3FFF is not configurable, always mapped to the internal palette control.