Difference between revisions of "Standard controller"

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m (Created page with 'All NES units come with at least one standard controller - without it, you wouldn't be able to play any games! Standard controllers can be used in both controller ports, or in a...')
 
(Evil Details)
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The CLK line for controller port is R/W nand (ADDRESS == $4016). When this transitions from high to low, the buffer inside the NES latches the output of the controller data lines, and when it transitions from low to high, the shift register in the controller shifts one bit.
 
The CLK line for controller port is R/W nand (ADDRESS == $4016). When this transitions from high to low, the buffer inside the NES latches the output of the controller data lines, and when it transitions from low to high, the shift register in the controller shifts one bit.
  
This can cause glitches if the DMC DMA is running, and happens to start a read in the same cycle that the CPU is trying to read from $4016 or $4017. Since the address bus will change for one cycle, the shift register will see an extra rising clock edge, and the shift register will drop a bit out. See http://nesdev.parodius.com/bbs/viewtopic.php?t=4116 for details.
+
This can cause glitches if the DMC DMA is running, and happens to start a read in the same cycle that the CPU is trying to read from $4016 or $4017. Since the address bus will change for one cycle, the shift register will see an extra rising clock edge, and the shift register will drop a bit out. See http://nesdev.parodius.com/bbs/viewtopic.php?t=4116 for details and http://nesdev.parodius.com/bbs/viewtopic.php?t=4124 for a reliable controller reading routine.

Revision as of 16:43, 14 March 2010

All NES units come with at least one standard controller - without it, you wouldn't be able to play any games!

Standard controllers can be used in both controller ports, or in a Four score accessory.

Input ($4016 write)

7  bit  0
---- ----
xxxx xxxS
        |
        +- Controller shift register strobe

Writing 1 to this bit will record the state of each button on the controller. Writing 0 afterwards will allow the buttons to be read back, one at a time.

Output ($4016/$4017 read)

7  bit  0
---- ----
xxxx xxxD
        |
        +- Serial controller data

The first 8 reads will indicate which buttons are pressed (1 if pressed, 0 if not pressed); all subsequent reads will return D=1 on an authentic controller but may return D=0 on third party controllers.

Button status for each controller is returned in the following order: A, B, Select, Start, Up, Down, Left, Right.

A Super NES controller can be wired to the NES controller port, and it returns button status in a similar order: B, Y, Select, Start, Up, Down, Left, Right, A, X, L, R.

Evil Details

The CLK line for controller port is R/W nand (ADDRESS == $4016). When this transitions from high to low, the buffer inside the NES latches the output of the controller data lines, and when it transitions from low to high, the shift register in the controller shifts one bit.

This can cause glitches if the DMC DMA is running, and happens to start a read in the same cycle that the CPU is trying to read from $4016 or $4017. Since the address bus will change for one cycle, the shift register will see an extra rising clock edge, and the shift register will drop a bit out. See http://nesdev.parodius.com/bbs/viewtopic.php?t=4116 for details and http://nesdev.parodius.com/bbs/viewtopic.php?t=4124 for a reliable controller reading routine.