Standard controller

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All NES units come with at least one standard controller - without it, you wouldn't be able to play any games!

Standard controllers can be used in both controller ports, or in a Four score accessory.

For code examples, see: Controller Reading

Input ($4016 write)

7  bit  0
---- ----
xxxx xxxS
        +- Controller shift register strobe

While S (strobe) is high, the shift registers in the controllers are continuously reloaded from the button states, and reading $4016/$4017 will keep returning the current state of the first button (A). Once S goes low, this reloading will stop. Hence a 1/0 write sequence is required to get the button states, after which the buttons can be read back one at a time.

(Note that bits 2-0 of $4016/write are stored in internal latches in the 2A03/07.)

Output ($4016/$4017 read)

NES-001 (front-loading NES) $4016 and $4017, and NES-101 (top-loading NES) $4016 and $4017
7  bit  0
---- ----
|||| ||||
|||| |||+- Serial controller data
|||+-+-+-- Always 0
|||   +--- Open bus on NES-101 $4016; 0 otherwise
+++------- Open bus
Famicom $4016:
7  bit  0
---- ----
oooo oMFD
|||| ||||
|||| |||+- Player 1 serial controller data
|||| ||+-- If connected to expansion port (and available), player 3 serial controller data (0 otherwise)
|||| |+--- Microphone in controller 2 on traditional Famicom, 0 on AV Famicom
++++-+---- Open bus
Famicom $4017:
7  bit  0
---- ----
|||| ||||
|||| |||+- Player 2 serial controller data
|||| ||+-- If connected to expansion port, player 4 serial controller data (0 otherwise)
|||+-+++-- Returns 0 unless something is plugged into the Famicom expansion port
+++------- Open bus

The first 8 reads will indicate which buttons are pressed (1 if pressed, 0 if not pressed). All subsequent reads will return D=1 on a Nintendo brand controller but may return D=0 on third party controllers such as the U-Force.

Button status for each controller is returned as an 8-bit report in the following order: A, B, Select, Start, Up, Down, Left, Right. On plug-in controllers (the NES and AV Famicom) and the first controller of the original Famicom, all buttons are present. However, on the original Famicom's second controller the Select and Start buttons are absent, and the encoder chip returns 0 instead: A, B, 0, 0, Up, Down, Left, Right. Because these buttons do not exist, games for the Famicom should never require the second player to press Select or Start.

In the NES and Famicom, the top three (or five) bits are not driven, and so retain the bits of the previous byte on the bus. Usually this is the most significant byte of the address of the controller port—0x40. Certain games (such as Paperboy) rely on this behavior and require that reads from the controller ports return exactly $40 or $41 as appropriate.

Due to the presence of internal pull-up resistors, and the internal inverter, any pin without power connected will return zero, as shown above in the diagrams.

Because the Famicom controllers are permanently attached, some games (such as Castlevania II - Simon's Quest) allow the use of the player 3 and 4 data for players 1 and 2.

A Super NES controller can be wired to the NES controller port, and it returns a 16-bit report in a similar order: B, Y, Select, Start, Up, Down, Left, Right, then A, X, L, R, and four 0 bits.


The 4021 (or 74LS165) IC is an 8-bit parallel-to-serial shift register. It has a pin "serial input", ordinarily used to chain the output of one shift register into the next one as seen in the Four Score or the Super NES controller. The serial input on the tail end of such a chain (or the only one in the case of an NES) can be tied to ground or Vcc, which determines the state of the output after all bits have been shifted out. If this is grounded, the shift register produces a 0 after all bits have been shifted out; if it's tied to Vcc, it produces a 1.

In the NES controller, this input is grounded. But because the signals from the controllers pass through an inverter before reaching the CPU, the register produces a 1 for all reads after the first eight.

APU DMC conflict glitch

The CLK line for controller port is R/W nand (ADDRESS == $4016/$4017) (i.e., CLK is low only when reading $4016/$4017, since R/W high means read). When this transitions from high to low, the buffer inside the NES latches the output of the controller data lines, and when it transitions from low to high, the shift register in the controller shifts one bit.[1]

This can cause glitches if the DMC DMA is running, and happens to start a read in the same cycle that the CPU is trying to read from $4016 or $4017. Since the address bus will change for one cycle, the shift register will see an extra rising clock edge (a "double clock"), and the shift register will drop a bit out. The program will see this as a bit deletion from the serial data. Not correcting for this results in spurious presses, especially of Right.

This glitch is fixed in the 2A07 CPU used in the PAL NES.

This detail is poorly represented in emulators. Because it is not normally a compatibility issue, many emulators do not simulate this glitch at all.

Multiple Read Solution

The standard solution used in most games using DMC will read the controller multiple times and compare the results to avoid this problem.

See Controller Reading for examples.

Synchronized OAM Solution

Because OAM DMA synchronizes the CPU and APU such that reads on an "even" CPU cycle never overlap a glitch, a program on an NTSC NES can miss all the glitches by triggering an OAM DMA as the last thing in vblank just before reading the controller, so long as all the reads are spaced an even number of cycles apart.[2]

Because this is a relatively new discovery, many current emulated implementations of the DMC glitch may be inadequate for testing this technique[3]. Hardware testing is recommended.


A turbo controller such as the NES Max or NES Advantage is read just like a standard controller, but the user can switch some of its buttons to be toggled by an oscillator. Such an oscillator turns the button on and off at 15 to 30 Hz, producing rapid fire in games.

A controller should not toggle the button states on each strobe pulse. Doing so will cause problems for games that poll the controller in a loop until they get two identical consecutive reads (see DMC conflict above). The game may halt while the turbo button is held, or crash, or cause other unknown behaviour.

See also


  1. Forum post: DPCM generates extra $4016 read pulse
  2. Forum post: Rahsennor's OAM-synchronized controller read
  3. Forum post: as of May 2016, Nintendulator and Nestopia do not accurately emulate OAM-synchronized controller reading.
  • Forum post: Famicom controller PCB and exterior photographs