Difference between revisions of "Talk:INES Mapper 001"

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m (Reverted edits by 91.237.249.29 (talk) to last revision by Ulfalizer)
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::It's likely that the writing mechanism might be ignoring M2. The only thing M2 is really needed for is enabling the PRG RAM chip. --[[User:Tepples|Tepples]] ([[User talk:Tepples|talk]]) 06:51, 19 March 2013 (MDT)
 
::It's likely that the writing mechanism might be ignoring M2. The only thing M2 is really needed for is enabling the PRG RAM chip. --[[User:Tepples|Tepples]] ([[User talk:Tepples|talk]]) 06:51, 19 March 2013 (MDT)
 
::Maybe someone should ask Disch, if he's easy to reach. I personally wouldn't mind people correcting mistakes in documents that are still credited to me. ;) --[[User:Ulfalizer|Ulfalizer]] ([[User talk:Ulfalizer|talk]]) 13:22, 19 March 2013 (MDT)
 
::Maybe someone should ask Disch, if he's easy to reach. I personally wouldn't mind people correcting mistakes in documents that are still credited to me. ;) --[[User:Ulfalizer|Ulfalizer]] ([[User talk:Ulfalizer|talk]]) 13:22, 19 March 2013 (MDT)
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:I wouldn't add this information on a "Kev says" basis, please test it first, or add a "big warning label" that it's just speculation. The reason I'm skeptical about it is the fact that MMC1 (seemingly) only ignores consecutive writes if the high bit of the first write is set. If it was edge-triggered, it would seem logical that the ignoring would also happen for non-reset writes. Then again, that, too, is just speculation (although parts of it have been tested on hardware). :) --[[User:Thefox|Thefox]] ([[User talk:Thefox|talk]]) 00:03, 14 July 2013 (MDT)

Revision as of 00:03, 14 July 2013

Would it be okay to add a note to Disch's note explaining the "too close together" behavior? Kev says it's due to edge-triggering.

The note would clearly indicate that it's an edit and not part of the original notes. -Ulfalizer (talk) 00:14, 19 March 2013 (MDT)

I'm torn about what to do with Disch's notes, especially when they're wrong. Sometimes I've just completely replaced them (iNES Mapper 234). Sometimes I've completely rewritten them (iNES Mapper 072). Sometimes I just put a big warning label at the top of the article (iNES Mapper 019). We don't have a standing policy of not editing Disch's notes, although I've accidentally caused confusion by not marking it when I've done so... oops.
Anyway, I'm not clear how edge triggered behavior causes what's happening here, unless the MMC1 ignores M2 altogether. —Lidnariq (talk) 01:33, 19 March 2013 (MDT)
It's likely that the writing mechanism might be ignoring M2. The only thing M2 is really needed for is enabling the PRG RAM chip. --Tepples (talk) 06:51, 19 March 2013 (MDT)
Maybe someone should ask Disch, if he's easy to reach. I personally wouldn't mind people correcting mistakes in documents that are still credited to me. ;) --Ulfalizer (talk) 13:22, 19 March 2013 (MDT)
I wouldn't add this information on a "Kev says" basis, please test it first, or add a "big warning label" that it's just speculation. The reason I'm skeptical about it is the fact that MMC1 (seemingly) only ignores consecutive writes if the high bit of the first write is set. If it was edge-triggered, it would seem logical that the ignoring would also happen for non-reset writes. Then again, that, too, is just speculation (although parts of it have been tested on hardware). :) --Thefox (talk) 00:03, 14 July 2013 (MDT)