INES Mapper 006

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iNES Mappers 006/008 are used for ROM images that have been converted from disk images for the Bung Game Doctor copiers. They are also supported by the Front FarEast Super Magic Card copiers. All of these ROM images have been extensively modified to use the copier's idiosyncratic bankswitch registers.

There are 32 KiB of CHR-RAM, enough to run games with less than or equal to that amount of CHR data with little modification. For games with more than 32 KiB of CHR-ROM, additional bankswitching code keeps track of the game's CHR-ROM bank usage and caches the most recently-used 32 KiB in CHR-RAM, copying data from PRG address space into CHR-RAM as needed. This necessarily involves screen flicker. The amount of extra code needed to accomplish this requires a "trainer" that is always loaded into PRG-RAM at $7000. According to the iNES format, this Trainer is supposedly always 512 bytes in size. A few ROM images however actually have 640- or 768-byte trainers, whose size must be detected as the modulus 8192 of the file size minus the 16 byte iNES header, detecting and ignoring any footer.

Banking Modes

The banking mode is changed via registers $42FE/$42FF. The initial banking mode upon startup would be directly available in the original disk image format that these copiers used, but can only be roughly deduced from the iNES header:

  • Mapper 002: Either actual INES Mapper 002 (UNROM/UOROM) or Copier Modes 0 (128 KiB PRG) or 2 (256 KiB PRG). Since actual UNROM/UOROM boards do not have PRG-RAM, any Mapper 002 iNES-format ROM image that has the Battery bit set, the Trainer bit set, or writes to $4024-$43FF is actually a Copier Mode 0/2 game.
  • Mapper 003: Either actual INES Mapper 003 (CNROM) or Copier Modes 5 (32 KiB CHR) or 7 (16 KiB CHR). Since actual CNROM boards do not have PRG-RAM, any Mapper 003 iNES-format ROM image that has the Battery bit set, the Trainer bit set, or writes to $4024-$43FF is actually a Copier Mode 5 game.
  • Mapper 006: Unspecified, but almost always Copier Mode 1.
  • Mapper 008: Copier Mode 4.

The initial nametable mirroring type can be deduced from the iNES header. Games that require one-screen mirroring, which could not be conveyed by the iNES header, always enable it by writing to $42FE themselves.

Mode 0: UNROM

  • 16 KiB PRG-ROM bank at CPU $8000-$BFFF, switched by D0..D7 of data latch at CPU $8000-$FFFF
  • 16 KiB PRG-ROM bank at CPU $C000-$FFFF, fixed to bank #7
  • 8 KiB of unbanked CHR-RAM

Mode 1: Custom

  • 16 KiB PRG-ROM bank at CPU $8000-$BFFF, switched by D2..D7 of data latch at CPU $8000-$FFFE (not $FFFF!)
  • 16 KiB PRG-ROM bank at CPU $C000-$FFFF, fixed to bank #7
  • 8 KiB CHR-RAM bank at PPU $0000-$1FFF, switched by D0..D1 of data latch at CPU $8000-$FFFE (not $FFFF!)

Mode 2: UOROM

  • 16 KiB PRG-ROM bank at CPU $8000-$BFFF, switched by D0..D7 of data latch at CPU $8000-$FFFF
  • 16 KiB PRG-ROM bank at CPU $C000-$FFFF, fixed to bank #15
  • 8 KiB of unbanked CHR-RAM

Mode 3: Reverse UOROM

  • 16 KiB PRG-ROM bank at CPU $8000-$BFFF, fixed to bank #15
  • 16 KiB PRG-ROM bank at CPU $C000-$FFFF, switched by D0..D7 of data latch at CPU $8000-$FFFF
  • 8 KiB of unbanked CHR-RAM
  • Seems to used by only one game (Kaiketsu Yanchamaru).

Mode 4: GNROM

  • 32 KiB PRG-ROM bank at CPU $8000-$FFFF, switched by D4..D5 of data latch at CPU $8000-$FFFF
  • 8 KiB CHR-RAM/ROM bank at PPU $0000-$1FFF, switched by D0..D1 of data latch at CPU $8000-$FFFF

Mode 5: CNROM (32 KiB CHR)

  • 32 KiB PRG-ROM bank at CPU $8000-$FFFF, fixed to bank #7
  • 8 KiB CHR-RAM/ROM bank at PPU $0000-$1FFF, switched by D0..D1 of data latch at CPU $8000-$FFFF

Mode 6: NROM-256/Protection

  • 32 KiB PRG-ROM bank at CPU $8000-$FFFF, fixed to bank #3
  • 8 KiB of unbanked CHR-RAM
  • Several ROM images set this mode to verify the content of a particular ROM location and will deliberately fail if it does not match.

Mode 7: CNROM (16 KiB CHR)/Protection

  • 32 KiB PRG-ROM bank at CPU $8000-$FFFF, fixed to bank #3
  • 8 KiB CHR-RAM/ROM bank at PPU $0000-$1FFF, switched by D0 of data latch at CPU $8000-$FFFF
  • Several ROM images set this mode to verify the content of a particular ROM location and will deliberately fail if it does not match.

4M Mode

  • 8 KiB PRG-ROM bank at CPU $8000-$9FFF, switched by D2..D7 of data latch at CPU $8000-$9FFF
  • 8 KiB PRG-ROM bank at CPU $A000-$BFFF, switched by D2..D7 of data latch at CPU $A000-$BFFF
  • 8 KiB PRG-ROM bank at CPU $C000-$DFFF, switched by D2..D7 of data latch at CPU $C000-$DFFF
  • 8 KiB PRG-ROM bank at CPU $E000-$FFFF, switched by D2..D7 of data latch at CPU $E000-$FFFF
  • 8 KiB CHR-RAM bank at PPU $0000-$1FFF, switched by D0..D1 of data latch at CPU $8000-$FFFF
  • 4M mode is enabled by writing any value to $43FE and disabled by writing any value to $43FF. If enabled, it has precedence over the eight banking modes set via $42FE-$42FF.
  • The four PRG bank registers are latched, even if not applied, when the 4M Mode is not active, and will take effect once $43FE is written to afterwards.

Global registers

Mirroring and 1M/2M Banking Mode ($42FC-$42FF)

A~FEDC BA98 7654 3210  D~7654 3210
  -------------------    ---------
  0100 0010 1111 11bM    BBBM ....
                   |+----|||+------ Set nametable mirroring type
                   |     |||         0: One-screen, page 0
                   |     |||         1: One-screen, page 1
                   |     |||         2: Vertical
                   |     |||         3: Horizontal
                   +-----|||------- 0: Ignore BBB bits, don't change banking mode
                         |||        1: Obey BBB bits, change banking mode
                         +++------- New banking mode if b==1 (see above)

4M Banking Mode Enable/Disable ($43FE-$43FF)

A~FEDC BA98 7654 3210
  -------------------
  0100 0011 1111 111M
                    +- Enable/Disable 4M Banking Mode
                        0: Enable
                        1: Disable

FDS Write Data ($4024)

This register is not part of the copier, but part of the FDS RAM adapter that attaches to it. A few games abusing the FDS Disk Data IRQ for frame timing write any value to this register to acknowledge a pending IRQ.

FDS Control ($4025)

This register is not part of the copier, but part of the FDS RAM adapter that attaches to it. A few games abuse the FDS Disk Data IRQ for frame timing. If bit 7 is set, the FDS RAM adapter will generate IRQs every 1,792 cycles of the 21.4772 MHz master clock, or after every 149+1/3 CPU cycles.

Cycle IRQ Counter Low Byte ($4100)

This is the low byte of a 16-bit counter that, if nonzero, is increased on every M2 cycle and raises an IRQ when the counter flips from $FFFF to $0000. Writing to this register also acknowledges the IRQ.

Cycle IRQ Counter High Byte ($4101)

This is the high byte of a 16-bit counter that, if nonzero, is increased on every M2 cycle and raises an IRQ when the counter flips from $FFFF to $0000.

Notes

  • Before control is transferred to the game's Reset handler vectored at $FFFC, the copier BIOS issues a JSR to $7003 if it finds a valid trainer there. This call is necessary to properly set up initial CHR-RAM content and bankswitching registers.
  • If a Mapper 006 ROM image specifies more than 32 KiB of CHR-ROM, then either it is not actually for Mapper 006, or those CHR-ROM banks need to be appended right after the PRG-ROM data.
  • At least one game (Ganbare Goemon Gaiden) has a trainer but also uses battery-backed RAM for saves. The startup routine (at $7003) moves the trainer to a safe location that the game does not use. To avoid overwriting saved game data, the trainer should therefore only be placed at $7000 if no SRAM file has been loaded.

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