INES Mapper 006

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iNES Mappers 006/008 are used for ROM images that have been converted from disk images for the Bung Game Doctor copiers. They are also supported by the Front FarEast Super Magic Card copiers. All of these ROM images have been extensively modified to use the copier's idiosyncratic bankswitch registers.

There are 32 KiB of CHR-RAM, enough to run games with less than or equal to that amount of CHR data with little modification. For games with more than 32 KiB of CHR-ROM, additional bankswitching code keeps track of the game's CHR-ROM bank usage and caches the most recently-used 32 KiB in CHR-RAM, copying data from PRG address space into CHR-RAM as needed. This necessarily involves screen flicker. The amount of extra code needed to accomplish this requires a "trainer" that is always loaded into PRG-RAM at $7000. According to the iNES format, this Trainer is supposedly always 512 bytes in size. A few ROM images however actually have 640- or 768-byte trainers, whose size must be detected as the modulus 8192 of the file size minus the 16 byte iNES header, detecting and ignoring any footer.

Banking Modes

The banking mode is changed via registers $42FE/$42FF. The initial banking mode upon startup would be directly available in the original disk image format that these copiers used, but can only be roughly deduced from the iNES header:

  • Mapper 002: Either actual INES Mapper 002 (UNROM/UOROM) or Copier Modes 0 (128 KiB PRG) or 2 (256 KiB PRG). Since actual UNROM/UOROM boards do not have PRG-RAM, any Mapper 002 iNES-format ROM image that has the Battery bit set, the Trainer bit set, or writes to $4024-$43FF is actually a Copier Mode 0/2 game.
  • Mapper 003: Either actual INES Mapper 003 (CNROM) or Copier Modes 5 (32 KiB CHR) or 7 (16 KiB CHR). Since actual CNROM boards do not have PRG-RAM, any Mapper 003 iNES-format ROM image that has the Battery bit set, the Trainer bit set, or writes to $4024-$43FF is actually a Copier Mode 5 game.
  • Mapper 006: Unspecified, but almost always Copier Mode 1.
  • Mapper 008: Copier Mode 4.

The initial nametable mirroring type can be deduced from the iNES header. Games that require one-screen mirroring, which could not be conveyed by the iNES header, always enable it by writing to $42FE themselves.

Mode 0: UNROM

  • 16 KiB PRG-ROM bank at CPU $8000-$BFFF, switched by D0..D2 of data latch at CPU $8000-$FFFF
  • 16 KiB PRG-ROM bank at CPU $C000-$FFFF, fixed to bank #7
  • 8 KiB of write-enabled CHR-RAM

Mode 1: Custom

  • 16 KiB PRG-ROM bank at CPU $8000-$BFFF, switched by D2..D6 of data latch at CPU $8000-$FFFE (not $FFFF!)
  • 16 KiB PRG-ROM bank at CPU $C000-$FFFF, fixed to bank #7
  • 8 KiB write-enabled CHR-RAM bank at PPU $0000-$1FFF, switched by D0..D1 of data latch at CPU $8000-$FFFE (not $FFFF!)

Mode 2: UOROM

  • 16 KiB PRG-ROM bank at CPU $8000-$BFFF, switched by D0..D3 of data latch at CPU $8000-$FFFF
  • 16 KiB PRG-ROM bank at CPU $C000-$FFFF, fixed to bank #15
  • 8 KiB of write-enabled CHR-RAM

Mode 3: Reverse UOROM

  • 16 KiB PRG-ROM bank at CPU $8000-$BFFF, fixed to bank #15
  • 16 KiB PRG-ROM bank at CPU $C000-$FFFF, switched by D0..D3 of data latch at CPU $8000-$FFFF
  • 8 KiB of write-enabled CHR-RAM
  • Seems to used by only one game (Kaiketsu Yanchamaru).

Mode 4: GNROM

  • 32 KiB PRG-ROM bank at CPU $8000-$FFFF, switched by D4..D5 of data latch at CPU $8000-$FFFF
  • 8 KiB write-protected CHR-RAM bank at PPU $0000-$1FFF, switched by D0..D1 of data latch at CPU $8000-$FFFF

Mode 5: CNROM-256

  • 32 KiB PRG-ROM bank at CPU $8000-$FFFF, fixed to bank #7
  • 8 KiB write-protected CHR-RAM bank at PPU $0000-$1FFF, switched by D0..D1 of data latch at CPU $8000-$FFFF

Mode 6: CNROM-128

  • 32 KiB PRG-ROM bank at CPU $8000-$FFFF, fixed to bank #3
  • 8 KiB of write-protected CHR-RAM bank at PPU $0000-$1FFF, switched by D0 of data latch at CPU $8000-$FFFF

Mode 7: NROM-256

  • 32 KiB PRG-ROM bank at CPU $8000-$FFFF, fixed to bank #3
  • 8 KiB write-protected CHR-RAM bank at PPU $0000-$1FFF, switched by D0 of data latch at CPU $8000-$FFFF

Notes

  • Unlike INES Mapper 002, the copier needs to differentiate between UNROM and UOROM because it has no other way of masking the PRG-ROM address to know which bank is the last bank.
  • CHR-RAM is write-protected in modes 4-7 and write-enabled in modes 0-3.
  • When changing from a mode that allows changing CHR-RAM banks to one that does not, the previously-chosen CHR-RAM bank remains active. The current CHR-RAM bank can be accessed directly, regardless of the selected 2M Mode, via register $43FF.
  • The latch at $8000-$FFFF is only active when PRG-ROM is write-protected.

4M PRG Mode

  • 8 KiB PRG-ROM bank at CPU $8000-$9FFF, switched by D2..D7 of data latch at CPU $8000-$9FFF
  • 8 KiB PRG-ROM bank at CPU $A000-$BFFF, switched by D2..D7 of data latch at CPU $A000-$BFFF
  • 8 KiB PRG-ROM bank at CPU $C000-$DFFF, switched by D2..D7 of data latch at CPU $C000-$DFFF
  • 8 KiB PRG-ROM bank at CPU $E000-$FFFF, switched by D2..D7 of data latch at CPU $E000-$FFFF
  • 8 KiB CHR-RAM bank at PPU $0000-$1FFF, switched by D0..D1 of data latch at CPU $8000-$FFFF
  • 4M mode is enabled by writing any value to $43FE and disabled by writing any value to $43FF. If enabled, it has precedence over the eight banking modes set via $42FE-$42FF. They still apply in one aspect only: whether CHR-RAM is write-enabled or not. This is used for effect by a few releases of games that originally wrote to CHR-ROM.
  • The four PRG bank registers are latched, even if not applied, when the 4M Mode is not active, and will take effect once $43FE is written to afterwards.

Global registers

Mirroring and 1M/2M Banking Mode ($42FC-$42FF)

A~FEDC BA98 7654 3210  D~7654 3210
  -------------------    ---------
  0100 0010 1111 11bM    BBBM ....
                   |+----|||+------ Set nametable mirroring type
                   |     |||         0: One-screen, page 0
                   |     |||         1: One-screen, page 1
                   |     |||         2: Vertical
                   |     |||         3: Horizontal
                   +-----|||------- 0: PRG-ROM is writeable, latch is disabled
                         |||        1: PRG-ROM is write-protected, latch is enabled
                         +++------- Banking mode (see above)

4M PRG Banking Mode Enable/Disable ($43FE-$43FF)

A~FEDC BA98 7654 3210  D~7654 3210
  -------------------    ---------
  0100 0011 1111 111M    ..PP p.CC
                    |      || | ++- Select 8 KiB CHR-RAM bank at PPU $0000-$1FFF
                    |      || +----*Select PRG A17 (128 KiB bank)
                    |      ++------*Select PRG A16/A15 (32/64 KiB bank)
                    |              *Ignored during gameplay, only used by BIOS
                    |               when loading a game from disk
                    +- Enable/Disable 4M PRG Banking Mode
                        0: Enable
                        1: Disable

FDS Write Data ($4024)

This register is not part of the copier, but part of the FDS RAM adapter that attaches to it. A few games abusing the FDS Disk Data IRQ for frame timing write any value to this register to acknowledge a pending IRQ.

FDS Control ($4025)

This register is not part of the copier, but part of the FDS RAM adapter that attaches to it. A few games abuse the FDS Disk Data IRQ for frame timing. If bit 7 is set, the FDS RAM adapter will generate IRQs every 1,792 cycles of the 21.4772 MHz master clock, or after every 149+1/3 CPU cycles.

Cycle IRQ Counter Low Byte ($4100)

This is the low byte of a 16-bit counter that, if nonzero, is increased on every M2 cycle and raises an IRQ when the counter flips from $FFFF to $0000. Writing to this register also acknowledges the IRQ.

Cycle IRQ Counter High Byte ($4101)

This is the high byte of a 16-bit counter that, if nonzero, is increased on every M2 cycle and raises an IRQ when the counter flips from $FFFF to $0000.

Notes

  • Before control is transferred to the game's Reset handler vectored at $FFFC, the copier BIOS issues a JSR to $7003 if it finds a valid trainer there. This call is necessary to properly set up initial CHR-RAM content and bankswitching registers.

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