INES Mapper 015
The iNES format assigns iNES Mapper 015 as the mapper used in 100-in-1 Contra Function 16, the first pirate multicart to be emulated.
The mapper allows multiple NROM or BNROM games plus one UNROM game to be used with very little modification. A few games originally released on a CNROM compatible board (such as two variants of Tetris) showed up on the cart; these were ripped to NROM by tossing out all 8 KB CHR banks except the one used for gameplay.
- PRG ROM size: Up to 1MB
- PRG ROM bank size: 8 KB, 16 KB, or 32 KB
- PRG RAM: 8 KB
- CHR capacity: 8 KB RAM
- CHR bank size: None
- Nametable mirroring: Controlled by mapper
- Subject to bus conflicts: No
There is one switchable bank. How this is mapped into depends on the current bank mode (see Registers below).
Bank mode 0 ( 32K )
- CPU $8000-$BFFF: Bank B
- CPU $C000-$FFFF: Bank (B bitwise ORed with 1)
If bit 0 of B equals 1, then the 16K and 32K modes are identical.
Bank mode 1 ( 128K )
- CPU $8000-$BFFF: Switchable 16 KB bank B
- CPU $C000-$DFFF:
Fixed to last bank in the cartKrzysiobal's reverse-engineered schematic says that this is B OR 7, and so supports multiple 128KiB UNROM games in one cart.
This mode uses the same configuration as UNROM.
Bank mode 2 ( 8K )
- CPU $8000-$9FFF: Sub-bank b of 16 KB PRG ROM bank B
- CPU $A000-$FFFF: Mirrors of $8000-$9FFF
Bank mode 3 ( 16K )
- CPU $8000-$BFFF: 16 KB bank B
- CPU $C000-$FFFF: Mirror of $8000-$BFFF
This is a 10-bit register. The upper 2 bits of the value are set from address lines A1-A0.
15 bit 8 7 bit 0 Address bus ---- ---- ---- ---- 1xxx xxxx xxxx xxSS | || | ++- Select PRG ROM bank mode | 0: 32K; 1: 128K (UNROM style); 2: 8K; 3: 16K +------------------- Always 1 7 bit 0 Data bus ---- ---- bMBB BBBB |||| |||| ||++-++++- Select 16 KB PRG ROM bank |+-------- Select nametable mirroring mode (0=vertical; 1=horizontal) +--------- Select 8 KB half of 16 KB PRG ROM bank (should be 0 except in 8K bank mode)
The result when b=1 outside of 8K bank mode is not specified. Some emulators (fceux, virtuanesex) are XORing the b (8KB half) bit frequently instead of ORing or ignoring. Krzysiobal's reverse-engineered schematic below states that the b bit is completely ignored except in mode 2.
All ten bits of this register are cleared on reset. This causes the first 32K to be mapped and mirroring to be vertical (PPUA10).
Krzysiobal's reverse-engineered schematic says that the CHR-RAM is write-protected when PRG mode is 0 or 3. It's unknown if there's another version of the same hardware with different behavior.
The unlicensed chinese WXN game Bio Hazard which uses this mapper freezes in the same way in fceux, fceu-mm, nestopia, bizhawk, and virtuanesx (maybe?) and so the game is probably buggy or actually on different hardware.