INES Mapper 105

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 Here are Disch's original notes:  
 =  Mapper 105          =
 Example Game:
 Nintendo World Championships 1990
 This mapper is an MMC1 with crazy wiring and a huge 30-bit CPU cycle driven IRQ counter.  Registers are all
 internal and not directly accessable -- and the latch must be written to 1 bit at a time -- just like on a
 normal MMC1.  For details on how regs are written to, see mapper 001.
 This mapper has 8k CHR-RAM, and it is not swappable.
 Note that like a normal MMC1, registers are internal and not accessed directly.
   $8000-9FFF:   [.... PSMM]  Same as MMC1 (but CHR mode bit isn't used)
   $A000-BFFF:   [...I OAA.]
        I = IRQ control / initialization toggle
        O = PRG Mode/Chip select
        A = PRG Reg 'A'
   $C000-DFFF:   [.... ....]  Unused
   $E000-FFFF:   [...W BBBB]
        W = WRAM disable (same as MMC1)
        B = PRG Reg 'B'
 Powerup / Reset / Initialization:
   On powerup and reset, the first 32k of PRG (from the first PRG chip) is selected at $8000 *no matter what*.
 PRG cannot be swapped until the mapper has been "initialized" by setting the 'I' bit to 0, then to '1'.  This
 toggling will "unlock" PRG swapping on the mapper.
   Note 'I' also controls the IRQ counter (see below)
 PRG Setup:
   There are 2 PRG chips, each 128k.  The 'O' bit selects between the chips, and also determines which PRG Reg
 is used to select the page.
   O=0:  Use first PRG chip (first 128k), use 'A' PRG Reg, 32k swap
   O=1:  Use second PRG chip (second 128k), use 'B' PRG Reg, MMC1 style swap
   In addition, if the mapper has not been "unlocked", the first 32k of the first chip is always selected
 regardless (as if $A000 contained $00).
   Modes as listed below:
                   $8000   $A000   $C000   $E000
 Uninitialized:  |             { 0 }             |  <-- use first 128k
 O=0:            |             $A000             |  <-- use first 128k
 O=1, P=0:       |            <$E000>            |  <-- use second 128k
 O=1, P=1, S=0:  |     { 0 }     |     $E000     |  <-- use second 128k
 O=1, P=1, S=1:  |     $E000     |     {$07}     |  <-- use second 128k
 IRQ Counter:
   The 'I' bit in $A000 controls the IRQ counter.  When cleared, the IRQ counter counts up every cycle.  When
 set, the IRQ counter is reset to 0 and stays there (does not count), and the pending IRQ is acknowledged.
   The cart has 4 dipswitches which control how high the counter must reach for an IRQ to be generated.
   The IRQ counter is 30 bits wide.. when it reaches the following value, an IRQ is fired:
   [1D CBAx xxxx xxxx xxxx xxxx xxxx xxxx]
     ^ ^^^
     | |||
     either 0 or 1, depending on the corresponding dipswitch.
 So if all dipswitches are open (use '0' above), the counter must reach $20000000.
 If all dipswitches are closed (use '1' above), the counter must reach $3E000000.
   In the official tournament, 'C' was closed, and the others were open, so the counter had to reach $2800000.