This chip was used at least in HK Famicom, Micro Genius IQ-201 (MK5060) , PC Engine (NEC MK5060-A) . Its role was to halt the PPU for 3.3 ms at the end of frame (but before the VBLANK). This was achieved by disabling the PPU's primary clock for that time. That way, frame period (NMI frequency) was extended from 16.7 ms (60 Hz) to 20 ms (50 Hz), slowing down the game and audio speed, but keeping PPU/CPU clock ratio and thus saving NTSC compatibility intact.
External components are used to extract from the composite video signal frame and scanline start pulses, which are used to clock the internal counter. At the last render scanline, chip puts PPU into sleep mode, which lasts 3.3ms. MK5060 also watches the PPU/CE line, probably in case if CPU requested to read/write from PPU at the time it is put into sleep, it would be immediately woken up. Additionally, if PPU rendering is disabled during frame, it fools MK5060.
.--\/--. high during frame sync & back porch ?? |01 24| -- +5V GND -- |02 23| ?? wired to pin 1 NC ?? |03 22| -- GND colorbust shift 240* <- |04 21| <- saturation input? colorbust shift 120* <- |05 20| -- +5V colorbust shift 0* <- |06 19| -> \ 21.x MHZ clock to PPU 21.x MHz clock from famicom -> |07 18| -> / high during frame sync <- |08 17| -> 4.43365 MHz clock output low during frame sync <- |09 16| <- 17.7345 MHz clock input PPU /CE -> |10 15| <- hue input? (?) 60Hz (H) / 50Hz (L) -> |11 14| <- scanline sync pulse (?) GND -- |12 13| -- +5V '------'