NES 2.0 submappers
Submapper is a term used in the NES 2.0 header for 4-bit codes designating functionally distinct variants of iNES mappers that cannot be distinguished by the memory size fields alone. Most emulators using iNES format distinguish these using CRC, SHA-1, or other hashes of the PRG ROM and CHR ROM, but this works only for games published prior to 1997, not for fan translations or ROM hacks, and not for new games on the same mapper.
Submapper 0 represents the default iNES behavour, so that backward compatibility is maintained with existing ROMs.
Submapper allocations that are listed as "deprecated" were assigned by kevtris' original proposal, but have no known use cases. The deprecation reserves these unused allocations to maintain continuity and compatibility.
This document is a living specification. Proposals for new submappers should be made at: Proposals.
- 1 001: MMC1
- 2 002, 003, 007: UxROM, CNROM, AxROM
- 3 004: MMC3
- 4 021, 023, 025: VRC2 / VRC4
- 5 032: Irem G101
- 6 034: BNROM / NINA-001
- 7 068: Sunsoft 4
- 8 071: Codemasters
- 9 078: Cosmo Carrier / Holy Diver
- 10 185: CNROM used to selectively disable CHR-ROM
- 11 210: Namco 175 and 340
- 12 232: Quattro
- 13 NES 2.0 Mapper 256
- 14 References
Boards with CHR-RAM usually reuse the CHR banking lines to address other things.
- SUROM, SOROM, and SXROM implement extra PRG-ROM and PRG-RAM banking (deprecated submappers 1, 2, 4).
- SNROM implements a redundant PRG-RAM enable (no assigned submapper).
Most boards with 32k of PRG-ROM have no PRG banking: SEROM, SHROM, SH1ROM (submapper 5).
001: 1, 2, 4 = SUROM, SOROM, SXROM
These submappers are a redundancy. The difference between these boards and the "normal" MMC1 implementation is exclusively dependent on the sizes of CHR, PRG RAM, and PRG ROM. Because of this, the addition of PRG RAM to the NES 2.0 specification was enough to make these compatible with submapper 0.
These three boards used 8k CHR RAM, and reused the CHR banking bits to bank PRG ROM and RAM instead. The specific boards can be detected by these sizes, or simply emulated together in submapper 0:
$A000 and $C000: 4bit0 ----- EDCBA ||||| ||||+- CHR A12 |||+-- CHR A13, if extant (CHR >= 16k) ||+--- CHR A14, if extant; and PRG RAM A14, if extant (PRG RAM = 32k, submapper 4) |+---- CHR A15, if extant; and PRG RAM A13, if extant (PRG RAM >= 16k, submappers 2, 4) +----- CHR A16, if extant; and PRG ROM A18, if extant (PRG ROM = 512k, submappers 1, 4)
The following games are on SUROM (submapper 1):
SOROM (submapper 2):
- Genghis Khan / Aoki Ookami to Shiroki Mejika: Genghis Khan
- Nobunaga's Ambition / Nobunaga no Yabou: Zenkokuban
- Romance of the Three Kingdoms / Sangokushi
SXROM (submapper 4):
- Final Fantasy I & II
- The Best Play Pro Yakyuu Special
- PR8. If extra RAM is missing, it gives a "DOES NOT WORK IN THIS EMULATOR" error.
If any NES 2.0 ROMs are found using these deprecated submappers, the CHR, PRG RAM, and PRG ROM sizes must appropriately match to be a valid header.
This originally described a submapper that was already implemented as iNES Mapper 155.
001: 5 Fixed PRG
PRG ROM A14 is connected directly to CPU A14 (and MMC1 A14 input) instead of MMC1 A14 output.
Existing games are compatible with submapper 0 if $8000-BFFF is initialized to the low bank, and $C000-FFFF is initialized to the high bank. These boards were used in several games: SEROM SHROM SH1ROM
Mappers 2, 3, and 7 describe discrete logic mappers that are usually subject to bus conflicts. Most of these games are programmed in a way that does not rely on the bus conflict behaviour, but software bugs may expose the difference (e.g. Cybernoid). Because these differences are obscure, the default iNES implementation for mappers 2 and 3 has been inconsistent across emulators, some with bus conflicts, some without. Mapper 7 is normally emulated without bus conflicts, because of a small number of games using the ANROM board which rely on this.
Two submappers allow this ambiguity to be resolved, by selecting a specific behaviour:
0: Default iNES behaviour (Emulators should warn the user and/or enforce bus conflicts for mappers 2 and 3, and should warn the user and/or fail to enforce bus conflicts for mapper 7)
1: Bus conflicts do not occur
2: Bus conflicts occur, producing the bitwise AND of the written value and the value in ROM
Although all Nintendo-manufactured games using normal CNROM (mapper 3), normal UxROM (mapper 2), and inverted UxROM (mapper 180) had bus conflicts, apparently several unlicensed games require their absence, as does the updated version of Donkey Kong with the pie factory level.
AxROM (mapper 7) is the only known licensed discrete logic mapper to unreliably come with bus conflict prevention circuitry. While no game documented in NesCartDB was released in one region on multiple board variants, several games did change boards when localized.
New ROMs are encouraged to specify submapper 2 to verify correct behaviour with bus conflicts.
CNROM with security diodes (mapper 185) has a different set of submapper definitions.
002: 0, 1, 2 UxROM
- 2_test_0.nes - Unspecified. (forum post)
- 2_test_1.nes - No bus conflicts. (forum post)
- 2_test_2.nes - AND bus conflicts. (forum post)
003: 0, 1, 2 CNROM
- 3_test_0.nes - Unspecified. (forum post)
- 3_test_1.nes - No bus conflicts. (forum post)
- 3_test_2.nes - AND bus conflicts. (forum post)
007: 0, 1, 2 AxROM
- 7_test_0.nes - Unspecified. (forum post)
- 7_test_1.nes - No bus conflicts. (forum post)
- 7_test_2.nes - AND bus conflicts. (forum post)
There are three known kinds of IRQ:
- MMC3A: IRQ is asserted on A12 rise, and loading the latch with 0 disables IRQ. Some chips labeled MMC3B also have this "old style" behavior. At least one unlicensed game relies on this behavior.
- MMC3C: IRQ is asserted on A12 rise, and loading the latch with 0 produces an IRQ on every scanline. Some chips labeled MMC3B also have this "new style" behavior, as does the MMC6. Some later games rely on this behavior.
- MC-ACC: IRQ is asserted on A12 fall, typically four pixels later than MMC3C. Interrupts can be produced every scanline, like the MMC3C.
There are two known kinds of PRG RAM enable:
- MMC3: One set of enable bits controls the entire chip.
- MMC6: The first and second enables control the first and second half of PRG RAM, and an additional enable in bit 5 of $8000 controls the whole PRG RAM.
The TEROM and TFROM boards have two jumpers that can respectively disable IRQs and force hard-wired mirroring. It is believed that nothing was ever released that used them.
004: 1 MMC6
MMC6 has an alternative PRG-RAM enable and write protection scheme designed for its internal 1k PRG RAM.
- StarTropics 2
This originally described MMC3C with hard wired mirroring. No games are known to require this.
004: 3 MC-ACC
The MC-ACC is found in 13 second-source PCBs manufactured by Acclaim:
- George Foreman's KO Boxing
- The Incredible Crash Dummies
- Mickey's Safari in Letterland
- Roger Clemens' MVP Baseball
- Rollerblade Racer
- The Simpsons: Bart vs. The World
- The Simpsons: Bartman Meets Radioactive Man
- Spider-Man: Return of the Sinister Six
- T&C Surf Designs 2: Thrilla's Surfari
- T2: Terminator 2: Judgment Day
- WWF King of the Ring
- WWF WrestleMania: Steel Cage Challenge
004: 4 MMC3A
Loading the latch with 0 disables IRQ.
- SuperGame's Aladdin (Mapper 4 version)
VRC2 is mostly a subset of VRC4, with differences including:
- VRC2 has a serial EEPROM interface which no Konami game ever connected an actual EEPROM to, but one PCB is wired so that it functions as a single bit of memory mapped at $6000-6FFF
- VRC4 supports horizontal, vertical and one-screen nametable mirroring while VRC2 supports only horizontal and vertical mirroring
- VRC4 supports two PRG ROM banking modes, similar to MMC3's. VRC2 only has one PRG ROM banking mode.
- VRC4 has an interrupt device that VRC2 does not.
Additionally, different boards connect the address lines for the registers in various arrangements. The three iNES mappers 21, 23, and 25 each combine multiple boards whose addresses overlap. This is enough for game compatibility, but it creates an ugly combination that does not accurately describe the original hardware of either board.
Konami's VRC2 and VRC4 mappers have several variations of how the board connects low CPU address lines among A7-A0 to the port select lines of the mapper. Mappers 21, 23 and 25 each combine two non-overlapping addressing variations, and neglect to specify VRC2 vs VRC4.
Mapper 22 is related, but only supports one variation (VRC2a) and has a different CHR banking arrangement than the others. It does not require submapper disambiguation.
|VRC2a||351618||A1||A0||$x000, $x002, $x001, $x003||22||0|
|VRC2b||many†||A0||A1||$x000, $x001, $x002, $x003||23||3|
|VRC2c||351948||A1||A0||$x000, $x002, $x001, $x003||25||3|
|VRC4a||352398||A1||A2||$x000, $x002, $x004, $x006||21||1|
|VRC4b||351406||A1||A0||$x000, $x002, $x001, $x003||25||1|
|VRC4c||352889||A6||A7||$x000, $x040, $x080, $x0C0||21||2|
|VRC4d||352400||A3||A2||$x000, $x008, $x004, $x00C||25||2|
|VRC4e||352396||A2||A3||$x000, $x004, $x008, $x00C||23||2|
|VRC4f||-||A0||A1||$x000, $x001, $x002, $x003||23||1|
- † The VRC2b PCBs include: 350603, 350636, 350926, 351179
This submapper assigment uses the following symmetrical arrangement:
- 0. Both addressing
- 1. Lower addressing, VRC4
- 2. Higher addressing, VRC4
- 3. Lower addressing, VRC2 (no known examples for mapper 21)
- 4. Higher addressing, VRC2 (no known examples)
021 / 023 / 025: 0
The default implementation acts as a VRC4 (mostly compatible superset of VRC2), and responds to register writes in one or more configurations simultaneously (supporting both boards at once).
021 / 023 / 025: 1, 2 VRC4
These allocations each request a single specific addressing scheme for VRC4, rather than the combined version used by submapper 0.
- 021: 1 VRC4a
- 025: 1 VRC4b
- 021: 2 VRC4c
- 025: 2 VRC4d
- 023: 2 VRC4e
- 023: 1 VRC4f
023: 1 VRC4f
Some unlicensed games used a second-source VRC4 clone with register addressing identical to VRC2b (the simplest contiguous in-order interpretation: 0,1,2,3). This was used in World Hero.
023: 3 VRC2b
Games on PCB 350926 (and its chip-on-board equivalents) rely on a single bit of RAM mapped in the region from $6000-$6FFF. Prior to NES 2.0, these games were supported by implementing WRAM in this region (despite this board not having WRAM). This board was used in Contra (J), Ganbare Goemon 2 and Konami Wai Wai World.
There are other VRC2 boards with the same register addressing as 350926 but without this feature ($6000-$6FFF is effectively open bus on them), but no game relies on the lack of the single bit of memory, so a separate submapper has not been allocated for them. These boards were used in Dragon Scroll, Getsu Fuuma Den, and Jarinko Chie.
Since this submapper represents VRC2, it should not implement the VRC4-only one-screen mirroring, PRG ROM banking modes, or IRQ capabilities. Wai Wai World depends on the lack of one-screen mirroring; it will have corrupt backgrounds in the vertically-scrolling stages and the ending if emulated with VRC4 capabilities.
025: 3 VRC2c
Ganbare Goemon Gaiden: Kieta Ougon Kiseru uses the same register addressing as VRC4b, but is VRC2, so this submapper should not implement VRC4-only capabilities.
032: Irem G101
A variation of this mapper requires hardwired one-screen mirroring and entirely ignores writes to $9000.
Normal (H/V mapper-controlled mirroring)
032: 1 Major League
CIRAM A10 is tied high (fixed one-screen mirroring) and PRG banking style is fixed as 8+8+16F
To disambiguate the two mappers, emulators have taken various approaches:
- The presense of CHR larger than 8 KiB unambiguously requires NINA-001, as BNROM has no CHR banking.
- The presence of CHR-RAM is taken to imply BNROM, because both extant BNROM games use CHR-RAM.
- CRC tests may be used to select a mapper for previously known ROMs.
- Implement both mappers simultaneously. This is compatible with existing games.
Selecting a single implementation based on CHR results in greater accuracy, since no game was ever intended for the combined definition.
New programs should not attempt to use a combined BNROM + NINA-001 mapper because this is not reliably available across emulators. Unusual combinations like NINA-001 with CHR-RAM are theoretically possible, but unlikely to be emulated consistently.
034: 1 NINA-001
034: 2 BNROM
Some unlicensed boards by Union Bond were a variation of BNROM that included PRG RAM. These may also use this submapper if PRG RAM is specified in the NES 2.0 header.
068: Sunsoft 4
In addition to its normal function, the Sunsoft 4 IC was used in Nantettatte!! Baseball, which allowed a second expansion cartridge to be plugged into it.
0: Normal (max 256KiB PRG)
068: 1 Dual Cartridge System
1: Sunsoft Dual Cartridge System a.k.a. NTB-ROM (max 128KiB PRG, licensing IC present, external option ROM of up to 128KiB should be selectable by a second menu)
Some games use this with 1-screen mirroring, where the mapper's mirroring control bit is wired directly to CIRAM A10. Others have hardwired horizontal or vertical mirroring.
Another variation of this mapper was used in the Quattro multicarts, but these have been reassigned to mapper 232.
Hardwired horizontal or vertical mirroring.
071: 1 Fire Hawk
Mapper controlled single-screen mirroring.
078: Cosmo Carrier / Holy Diver
This mapper unfortunately combines two games with incompatible mirroring control.
One game uses this with 1-screen mirroring, where the mapper's mirroring control bit is wired directly to CIRAM A10. The other can switch between horizontal and vertical mirroring, using a multiplexer between PPU A10 and PPU A11 whose output is sent to CIRAM A10.
078: 1 Cosmo Carrier
Single-screen mirroring (nibble-swapped mapper 152).
This described a variation with fixed vertical mirroring, and WRAM. There is no known use case.
078: 3 Holy Diver
Mapper-controlled H/V mirroring.
185: CNROM used to selectively disable CHR-ROM
A few NROM-like games were released on CNROM boards where all four bits of the latch were solely used as an anti-piracy measure. Games would check that CHR-ROM is disabled unless the latch holds the correct one of the four possible bank values. See this thread for test ROMs and example implementation code.
Correct bank value unknown. A heuristic that works with all known games that use this mapper is to return $FF on the first two reads from CPU $2007 after a reset.
Enable CHR-ROM if bits 0..1 of the latch hold the value 0, otherwise disable CHR-ROM.
Enable CHR-ROM if bits 0..1 of the latch hold the value 1, otherwise disable CHR-ROM.
Enable CHR-ROM if bits 0..1 of the latch hold the value 2, otherwise disable CHR-ROM.
Enable CHR-ROM if bits 0..1 of the latch hold the value 3, otherwise disable CHR-ROM.
210: Namco 175 and 340
Mapper 210 doesn't distinguish between the 175's hardwired mirroring and 340's 1/H/V mirroring.
Also, previous confusion and compatibility code used by Namco when they were developing games means that many 175- and 340- using games are incorrectly tagged as mapper 19.
No advisory statement is made (use runtime heuristics suggested at mapper 210)
210: 1 N175
Namco 175. Hardwired mirroring, no IRQ.
- Famista '91
- Family Circuit '91
- Chibi Maruko-chan: Uki Uki Shopping
- Heisei Tensai Bakabon / Genius Bakabon
210: 2 N340
Namco 340. 1/H/V mirroring, no IRQ, no internal or external RAM.
- Wagyan Land 2
- Famista '92
- Dream Master
- Top Striker
- Wagyan Land 3
- Famista '93
- Famista '94
Similar to #71 above, with a separate register controlling which 64 KiB outer bank of the PRG ROM is used. This is used for the Quattro multicarts.
The Aladdin Deck Enhancer version of these multicarts used a different banking scheme.
232: 1 Aladdin Deck Enhancer
Aladdin Deck Enhancer variation. Swap the bits of the outer bank number.
- Quattro Adventure (Aladdin Deck Enhancer)
- Quattro Sports (Aladdin Deck Enhancer)
- Pegasus 4-in-1
- Super Adventure Quests (European release of Quattro Adventure)
Several plug-and-play consoles use a simple protection scheme intended to prevent interchanging the ROM data between different consoles. The protection scheme works by simply swapping the addresses of the bankswitch registers. Some patterns only change the VTxx-native register addresses, others apply to the MMC3 compatibility registers as well.
|Submapper #||Name||PPU bank affected by ...||CPU bank affected by ...|
|2||Power Joy Supermax||$1000||$1400||$1800||$1C00||$0000||$0800||$0000||$0800||$1000||$1400||$1800||$1C00||$A000||$8000||$A000||$8000|
|4||Sports Game 69-in-1||$1800||$0800||$1000||$0000||$1C00||$1400||$0000||$0800||$1000||$1400||$1800||$1C00||$8000||$A000||$8000||$A000|