Talk:INES Mapper 047

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Oversize definition

It would be nice to define this as "the latch controls the MSB of both PRG and CHR addresses" instead of always A17. This would make it trivial to get a RAMless oversize MMC3 with 1MiB PRG and 512KiB CHR. —Lidnariq (talk) 02:18, 15 September 2013 (MDT)

A competing oversize definition would be to keep each segment 128K and add more bits to the latch. For example 4 bits would give 16 banks, or 2 MiB PRG and 2 MiB CHR. --Tepples (talk) 06:41, 15 September 2013 (MDT)