VTxx

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VTxx refers to V.R. Technology's "NES-on-a-chip" Famiclones, some of which having greatly extended capabilities. These capabilities are described in separate articles:

VTxx-numbered Famiclones, with two digits after "VT", are backwards-compatible to lower-numbered models as well as the original NES/Famicom, with a few exceptions. VTxxx-numbered consoles, with three digits after "VT", drop compatibility to the original NES/Famicom.

Memory Map

CPU Memory Map

CPU $0000-$07FF: 2 KiB of internal RAM
CPU $0800-$0FFF: VT16+: VT01-VT03: Mirror of CPU $0000-$07FF, VT16+: Further 2 KiB of internal RAM
CPU $1000-$1FFF: Mirror of CPU $0000-$0FFF
CPU $2000-$2007: RP2C02-compatible PPU registers
CPU $2010-$201F: VT02+: New PPU registers
CPU $4000-$401F: RP2A03-compatible APU, DMA and I/O registers
CPU $4020-$403F: VT02+: New APU, DMA and I/O registers
CPU $4100-$41FF: VT02+: New miscellaneous registers
CPU $6000-$7FFF: Optional WRAM, if present on cartridge
CPU $8000-$FFFF (write): VT02+: When forwarding is enabled (register $410B bit 3 "FWEN" =0): MMC3-compatible registers that are forwarded to $4101-$4108)
CPU $8000-$FFFF (read): Four 8 KiB PRG-ROM banks.

PPU Memory Map

PPU $0000-$1FFF: CHR-ROM, all modes: CHR pattern data, bit planes 0 and 1
PPU $2000-$2FFF: NTRAM (2 KiB, selectable mirroring)
PPU $3F00-$3F1F: CGRAM in 2bpp modes, entries $3F10/$3F14/$3F18/$3F01 mirrors of $3F00/$3F04/$3F08/$3F0C.
                 VT03+: Also CGRAM in 4bpp modes, bits 0 to 5, of colors 00-1F; same mirroring of address bit 4 applies.
PPU $3F20-$3F7F: VT03+: CGRAM in 4bpp modes, bits 0 to 5, of colors 20-7F; no mirroring of address bit 4.
PPU $3F80-$3FFF: VT03+: CGRAM in 4bpp modes, bits 6 to 11, of colors 00-7F; no mirroring of address bit 4.
PPU $4000-$5FFF: CHR-ROM, 4bpp modes: CHR pattern data, bit planes 2 and 3 (VT03+)

List of VTxx consoles

VT01

The VT01 is V.R. Technology's first Famiclone. Its only enhancement is the ability to drive an STN display directly using a modified palette.

VT02

The first of the V.R. Technology Famiclones to add major enhancements:

  • OneBus mode: PRG and CHR data come from the same address space. The cartridge connector's PPU Address lines are repurposed as higher-order Address lines.
  • Integrated MMC3-compatible bankswitching by the console, active when in OneBus mode.
  • Ability to use NTRAM as CHR-RAM.
  • Choice of PPU A12 and HBLANK as a source for clocking the scanline interrupt.
  • Automatic X/Y light gun position determination.
  • Integrated RS232 interface.
  • Direct NTSC/PAL and 50/60 Hz identification.
  • Automatic per-attribute-tile background and per-sprite sprite bankswitching.
  • DMA can be used to transfer data to PPU memory (via $2007) in addition to the normal transferring of data to OAM memory (via $2004).
  • A second APU doubling the number of sound channels.
  • Raw PCM output using full eight bits of resolution.
  • DMA-driven raw PCM output.
  • Data for DMA-driven DPCM/PCM output can be placed anywhere in CPU address space, not just within the $C000-$FFFF range.

VT03

The VT03 greatly enhances the graphical capabilities of the original RP2C02:

  • Sprites can be 16 pixels wide.
  • Graphics can use four bits-per-pixel, so that together with two attribute data bits, sixty-four rather than 16 colors each for background and sprites may be chosen.
  • Enhanced color palette with twelve bits rather than six bits per color.

VT09, VT16, VT18

The VT16 is the first of the NES-compatible Famiclones after the VT03 for which a datasheet is publicly available. It is likely however that many of its enhancements were already included in the VT09 console.

  • Internal CPU RAM is 4 KiB rather than just 2 KiB.
  • The CPU can be set to run at the same speed (5.37 MHz) as the PPU.
  • The CPU can be set to retrieve interrupt vectors from RAM ($0FFx) rather than ROM ($FFFx).
  • DMA-driven DPCM/PCM output can be set to use its own banking registers independent of normal PRG banking.
  • Hardware random number generator.

References