Difference between revisions of "Controller reading"

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(putting up a temporary stub in case someone comes here while I'm editing right now)
(turning this article into a general reference for controller interface on the NES)
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This article is undergoing an edit to summarize elements of [[Standard controller]] and [[Controller reading code]] to describe the controller interface for the NES. Please see those articles instead while this is in progress.
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NES and Famicom controllers are operated through a register interface that is connected to the [[Controller port pinout|controller port]] and [[expansion port]], as well as hardwired controllers on the Famicom.
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For most [[input devices]] a standard procedure is used for reading input:
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# Write 1 to $4016 to signal the controller to poll its input
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# Write 0 to $4016 to finish the poll
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# Read polled data one bit at a time from $4016 or $4017
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== $4016 Write ==
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7  bit  0
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---- ----
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xxxx xEES
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      |||
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      ||+- Controller port latch bit
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      ++-- Expansion port latch bits
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The low 3 bits written to this register will be latched and held. Its output will be continuously available on the OUT line of the [[Controller port pinout|controller port]], and the [[expansion port]].
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Other bits are ignored.
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On the [[standard controller]] this is connected to the PARALLEL/SERIAL CONTROL of a 4021 8-bit shift register. Writing 1 to $4016 causes the register to fill its parallel inputs from the buttons currently held. Writing 0 to $4016 returns it to serial mode, waiting to be read out one bit at a time. Most other [[input devices]] operate in a similar way.
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== $4016 / $4017 Read ==
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7  bit  0
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---- ----
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xxxD DDDD
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|||+-++++- Input data lines D4 D3 D2 D1 D0
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+++------- Open bus
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Reading from this register causes a clock pulse to be sent to the [[Controller port pinout|controller port]] CLK line on one controller, and one bit will be read from the connected input lines. $4016 reads only from controller port 1, and $4017 reads only from controller port 2. The read value is inverted: a high signal from the data line will read as 0, and a low signal will read as 1.
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For most devices it is necessary to read several times from these registers to collect multiple output bits from the device.
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The specific use of each data line depends on the [[Input devices|input device]] connected. For the standard controller and zapper which commonly came with the NES/Famicom:
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D0 - NES [[standard controller]], Famicom hardwired controller
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D1 - Famicom expansion port controller
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D2 - Famicom microphone (controller 2 only)
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D3 - [[Zapper]] light sense
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D4 - Zapper trigger
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The NES [[Controller port pinout|controller port]] makes only D0, D3 and D4 available for peripherals. The Famicom hardwired controllers connect to D0, and $4017.D2 (microphone) only. The other lines can be connected through the [[expansion port]] on the Famicom. The NES expansion port was never used commercially, but also connects these other lines.
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=== Clock timing ===
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The CLK line for controller port is ''R/W nand (ADDRESS == $4016/$4017)'' (i.e., CLK is low only when reading $4016/$4017, since R/W high means read). When this transitions from high to low, the buffer inside the NES latches the output of the controller data lines, and when it transitions from low to high, the shift register in the controller shifts one bit.<ref>[//forums.nesdev.com/viewtopic.php?t=4116 Forum post:] DPCM generates extra $4016 read pulse</ref>
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=== DPCM Conflict ===
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(Not yet written. See [[Standard controller]].)
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=== Unconnected data lines and open bus ===
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The behaviour of unconnected lines is more complicated. Often it involves [[open bus]] behaviour.
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(Not yet written. See [[Standard controller]].)
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== See Also ==
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* [[Controller reading code]]
 
* [[Standard controller]]
 
* [[Standard controller]]
* [[Controller reading code]]
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* [[Input devices]]
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== References ==
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<References/>

Revision as of 23:21, 20 April 2019

NES and Famicom controllers are operated through a register interface that is connected to the controller port and expansion port, as well as hardwired controllers on the Famicom.

For most input devices a standard procedure is used for reading input:

  1. Write 1 to $4016 to signal the controller to poll its input
  2. Write 0 to $4016 to finish the poll
  3. Read polled data one bit at a time from $4016 or $4017

$4016 Write

7  bit  0
---- ----
xxxx xEES
      |||
      ||+- Controller port latch bit
      ++-- Expansion port latch bits

The low 3 bits written to this register will be latched and held. Its output will be continuously available on the OUT line of the controller port, and the expansion port.

Other bits are ignored.

On the standard controller this is connected to the PARALLEL/SERIAL CONTROL of a 4021 8-bit shift register. Writing 1 to $4016 causes the register to fill its parallel inputs from the buttons currently held. Writing 0 to $4016 returns it to serial mode, waiting to be read out one bit at a time. Most other input devices operate in a similar way.

$4016 / $4017 Read

7  bit  0
---- ----
xxxD DDDD
|||+-++++- Input data lines D4 D3 D2 D1 D0
+++------- Open bus

Reading from this register causes a clock pulse to be sent to the controller port CLK line on one controller, and one bit will be read from the connected input lines. $4016 reads only from controller port 1, and $4017 reads only from controller port 2. The read value is inverted: a high signal from the data line will read as 0, and a low signal will read as 1.

For most devices it is necessary to read several times from these registers to collect multiple output bits from the device.

The specific use of each data line depends on the input device connected. For the standard controller and zapper which commonly came with the NES/Famicom:

D0 - NES standard controller, Famicom hardwired controller
D1 - Famicom expansion port controller
D2 - Famicom microphone (controller 2 only)
D3 - Zapper light sense
D4 - Zapper trigger

The NES controller port makes only D0, D3 and D4 available for peripherals. The Famicom hardwired controllers connect to D0, and $4017.D2 (microphone) only. The other lines can be connected through the expansion port on the Famicom. The NES expansion port was never used commercially, but also connects these other lines.

Clock timing

The CLK line for controller port is R/W nand (ADDRESS == $4016/$4017) (i.e., CLK is low only when reading $4016/$4017, since R/W high means read). When this transitions from high to low, the buffer inside the NES latches the output of the controller data lines, and when it transitions from low to high, the shift register in the controller shifts one bit.[1]

DPCM Conflict

(Not yet written. See Standard controller.)

Unconnected data lines and open bus

The behaviour of unconnected lines is more complicated. Often it involves open bus behaviour.

(Not yet written. See Standard controller.)

See Also

References

  1. Forum post: DPCM generates extra $4016 read pulse