Difference between revisions of "NES 2.0 Mapper 534"

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($6002 with Lock bit)
(CNROM-128 mode)
Line 38: Line 38:
  
 
==Inner CHR Bank Register ($6002, write)==
 
==Inner CHR Bank Register ($6002, write)==
  Mask: $E803
+
  Mask: $E003
 
   
 
   
 
  D~7654 3210
 
  D~7654 3210
 
   ---------
 
   ---------
   .... CCCC
+
   ...M CCCC
        ++++- CHR A16..A13 in CNROM mode,
+
      | ++++- CHR A16..A13 in CNROM mode,
              ignored otherwise
+
      |      ignored otherwise
 +
      +------ 1=CNROM-128 mode, 0=CNROM-256 mode
  
 +
The CNROM bit matters when the Lock bit is set: In CNROM-256 mode, bits 0 and 1 are still writable, in CNROM-128 mode, only bit 0 is writable.
 
==Mode Register ($6003, write)==
 
==Mode Register ($6003, write)==
 
  Mask: $E003
 
  Mask: $E003
Line 60: Line 62:
 
   |          0: MMC3
 
   |          0: MMC3
 
   |          1: CNROM
 
   |          1: CNROM
   +--------- Lock registers $6000 and $6003
+
   +--------- Lock registers $6000-$6003 except $6002.0/1
  
 
NROM PRG banking mode is implemented by holding the MMC3 clones' CPU A13 and A14 input low. This means that...
 
NROM PRG banking mode is implemented by holding the MMC3 clones' CPU A13 and A14 input low. This means that...
Line 72: Line 74:
 
==Note==
 
==Note==
 
* Outer bank registers overlay any WRAM, and can only be written to if WRAM is enabled in the MMC3 ($A001=$80).
 
* Outer bank registers overlay any WRAM, and can only be written to if WRAM is enabled in the MMC3 ($A001=$80).
* Register $6002 bits 0-1 are not affected by the Lock bit in register $6003.
+
* Register $6002 bit 0, and 1 in CNROM-256 mode, are not affected by the Lock bit in register $6003.
 
* [[INES Mapper 126]] is almost identical. It connects the higher CHR address lines differently, and MMC3 register $C000 functions normally.
 
* [[INES Mapper 126]] is almost identical. It connects the higher CHR address lines differently, and MMC3 register $C000 functions normally.

Revision as of 09:09, 31 January 2021

NES 2.0 Mapper 534 denotes an MMC3-based multicart mapper with an optional (C)NROM-like PRG and CHR banking modes.

  • Atari Flashback Mini 7800
  • TV Play Power - Intellivision 25-in-1
  • 2-in-1 数独/五子棋 (NJ064) by Shenzhen Nanjing
  • 18-in-1 Educational Computer by Zhuhai S.E.Z. Liming Electronic Co. Ltd.
  • 8-in-1 (kk3311) by Waixing
  • 8-in-1 (kk3314) by Waixing
  • 101-in-1 (a variant of which uses INES Mapper 045).

MMC3-compatible registers ($8000-$FFFF, write)

These registers function identically to a normal MMC3, except that the scanline counter latch register ($C000) takes the inverted value (XOR $FF) compared to a regular MMC3.

Outer Bank/PRG Mask Register ($6000, write)

Mask: $E003

D~7654 3210
  ---------
  XYBB CPPp
  |||| |||+- PRG A17 if Y=1
  ||++-|+++- PRG A21..A18
  ||++-+---- CHR A19..A17
  |+-------- PRG A17 mode
  |           0: PRG A17=MMC3 PRG A17 (256 KiB inner PRG bank size)
  |           1: PRG A17=p (128 KiB inner PRG bank)
  +--------- CHR A17 mode
              0: CHR A17=MMC3 CHR A17 (256 KiB inner CHR bank size)
              1: CHR A17=C (128 KiB inner CHR bank)

Miscellaneous Register ($6001, write)

Mask: $E003

D~7654 3210
  ---------
  .... ..?M
          +- 0: CPU $8000-$FFFF reads PRG-ROM
             1: CPU $8000-$FFFF reads solder pad (D0/D1)

Inner CHR Bank Register ($6002, write)

Mask: $E003

D~7654 3210
  ---------
  ...M CCCC
     | ++++- CHR A16..A13 in CNROM mode,
     |       ignored otherwise
     +------ 1=CNROM-128 mode, 0=CNROM-256 mode

The CNROM bit matters when the Lock bit is set: In CNROM-256 mode, bits 0 and 1 are still writable, in CNROM-128 mode, only bit 0 is writable.

Mode Register ($6003, write)

Mask: $E003

D~7654 3210
  ---------
  L..C .?PP
  |  |   ++- PRG Banking Mode
  |  |        0: MMC3
  |  |        1: NROM-128: PRG A14=MMC3 PRG A14
  |  |        2: NROM-128: Same as 1
  |  |        3: NROM-256: PRG A14=CPU A14
  |  +------ CHR Banking Mode
  |           0: MMC3
  |           1: CNROM
  +--------- Lock registers $6000-$6003 except $6002.0/1

NROM PRG banking mode is implemented by holding the MMC3 clones' CPU A13 and A14 input low. This means that...

  • MMC3 register #6 applies across the entire CPU $8000-$FFFF address range;
  • the MMC3's PRG A13 output is substituted with CPU A13;
  • in NROM-256 mode, the MMC3's PRG A14 output substituted with CPU A14;
  • MMC3 $8000.6 bits 1-3 therefore select a 16 KiB inner bank number.

CNROM CHR banking mode is implemented by using register $6002 as a source for an 8 KiB inner bank number instead of the MMC3's CHR registers.

Note

  • Outer bank registers overlay any WRAM, and can only be written to if WRAM is enabled in the MMC3 ($A001=$80).
  • Register $6002 bit 0, and 1 in CNROM-256 mode, are not affected by the Lock bit in register $6003.
  • INES Mapper 126 is almost identical. It connects the higher CHR address lines differently, and MMC3 register $C000 functions normally.