Difference between revisions of "NTDEC TC-112 pinout"

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(Copy BootGod's pinout from forum)
 
(explain what CHR1 and CHR2 is)
 
(7 intermediate revisions by one other user not shown)
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NTDEC TC-112: 40-pin 0.6" PDIP. (Canonically [[iNES Mapper 193]])
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[[Category:Pinouts]]NTDEC TC-112: 40-pin 0.6" PDIP. (Canonically [[iNES Mapper 193]])
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                .---\/---.
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  (n)      M2 -> |1    40| -- VCC
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  (nr) CPU D7 -> |2    39| -> PRG A16  (r)
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  (nr) CPU D6 -> |3    38| -> PRG A15  (r)
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  (nr) CPU D5 -> |4    37| -> PRG A14  (r)
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  (nr) CPU D4 -> |5    36| -> PRG A13  (r)
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  (nr) CPU D3 -> |6    35| -> PRG /CE  (r)
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  (nr) CPU D2 -> |7    34| -> CHR A17  (r)
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  (nr) CPU D1 -> |8    33| -> CHR A16  (r)
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  (nr) CPU A1 -> |9    32| -> CHR A15  (r)
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  (nr) CPU A0 -> |10    31| -> CHR A14  (r)
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  (n) CPU R/W -> |11    30| -> CHR A13  (r)
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  (n) CPU /CE -> |12    29| -> CHR A12  (r)
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  (n) CPU A14 -> |13    28| -> CHR A11  (r)
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  (n) CPU A13 -> |14    27| -> CHR1 /CE (r) = (PPU /RD) or (PPU A13) or (CHR A17)
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  (n) PPU A13 -> |15    26| -> CHR2 /CE (r) = (PPU /RD) or (PPU A13) or (not CHR A17)
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  (n) PPU A12 -> |16    25| <- CPU D0  (nr)
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  (n) PPU A11 -> |17    24| -> /W6005
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  (nr)PPU A10 -> |18    23| -> /W6006
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  †  PPU /RD -> |19    22| <- CPU A2  (nr)
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          GND -- |20    21| -> CIRAM A10 (n)
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                `--------'
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† On one board, connected to a seemingly-needlessly-complicated [[7400]] circuit. See the [http://forums.nesdev.com/viewtopic.php?t=7106 thread on the forum].
  
C = Connected to cart
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R = Connected to ROM
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Sources:
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* BootGod: https://forums.nesdev.com/viewtopic.php?p=69275#p69275
            ---------
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* Krzysiobal: https://forums.nesdev.com/viewtopic.php?t=19751
C      M2 -|1    40|- VCC
 
CR CPU  D7 -|2    39|- PRG A16 R
 
CR CPU  D6 -|3    38|- PRG A15 R
 
CR CPU  D5 -|4    37|- PRG A14 R
 
CR CPU  D4 -|5  N 36|- PRG A13 R
 
CR CPU  D3 -|6  T 35|- PRG /CE R
 
CR CPU  D2 -|7  D 34|- NC
 
CR CPU  D1 -|8  E 33|- CHR A16 R
 
CR CPU  A1 -|9  C 32|- CHR A15 R
 
CR CPU  A0 -|10  31|- CHR A14 R
 
C  CPU R/W -|11 T 30|- CHR A13 R
 
C  CPU /CE -|12 C 29|- CHR A12 R
 
C  CPU A14 -|13 - 28|- CHR A11 R
 
C  CPU A13 -|14 1 27|- CHR /CE R
 
C  PPU A13 -|15 1 26|- NC
 
C  PPU A12 -|16 2 25|- CPU D0  RC
 
C  PPU A11 -|17  24|- NC
 
CR PPU A10 -|18  23|- NC
 
74LS00  3Y -|19  22|- CPU A2  RC  eh?
 
        GND -|20  21|- NC
 
            ---------
 

Latest revision as of 17:12, 12 June 2021

NTDEC TC-112: 40-pin 0.6" PDIP. (Canonically iNES Mapper 193)

                .---\/---.
 (n)      M2 -> |1     40| -- VCC
 (nr) CPU D7 -> |2     39| -> PRG A16  (r)
 (nr) CPU D6 -> |3     38| -> PRG A15  (r)
 (nr) CPU D5 -> |4     37| -> PRG A14  (r)
 (nr) CPU D4 -> |5     36| -> PRG A13  (r)
 (nr) CPU D3 -> |6     35| -> PRG /CE  (r)
 (nr) CPU D2 -> |7     34| -> CHR A17  (r)
 (nr) CPU D1 -> |8     33| -> CHR A16  (r)
 (nr) CPU A1 -> |9     32| -> CHR A15  (r)
 (nr) CPU A0 -> |10    31| -> CHR A14  (r)
 (n) CPU R/W -> |11    30| -> CHR A13  (r)
 (n) CPU /CE -> |12    29| -> CHR A12  (r)
 (n) CPU A14 -> |13    28| -> CHR A11  (r)
 (n) CPU A13 -> |14    27| -> CHR1 /CE (r) = (PPU /RD) or (PPU A13) or (CHR A17)
 (n) PPU A13 -> |15    26| -> CHR2 /CE (r) = (PPU /RD) or (PPU A13) or (not CHR A17)
 (n) PPU A12 -> |16    25| <- CPU D0  (nr)
 (n) PPU A11 -> |17    24| -> /W6005
 (nr)PPU A10 -> |18    23| -> /W6006
  †  PPU /RD -> |19    22| <- CPU A2  (nr)
         GND -- |20    21| -> CIRAM A10 (n)
                `--------'

† On one board, connected to a seemingly-needlessly-complicated 7400 circuit. See the thread on the forum.


Sources: