Difference between revisions of "VRC3 pinout"

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m (omit now-redundant link to redirect)
(KS202 pinout probably belongs here?)
Line 7: Line 7:
 
   (r) PRG A16 <- |01 18| -- +5V
 
   (r) PRG A16 <- |01 18| -- +5V
 
   (r) PRG /CE <- |02 17| -> WRAM /CE (w)
 
   (r) PRG /CE <- |02 17| -> WRAM /CE (w)
   (r) PRG A14 <- |03 16| <- CPU RnW  (wfr)
+
   (r) PRG A14 <- |03 16| <- R/W      (wfr)
 
   (r) PRG A15 <- |04 15| <- CPU D3  (wfr)
 
   (r) PRG A15 <- |04 15| <- CPU D3  (wfr)
   (f) CPU M2 -> |05 14| <- CPU D0  (wfr)
+
   (f)     M2 -> |05 14| <- CPU D0  (wfr)
 
  (wfr) CPU A12 -> |06 13| <- CPU D1  (wfr)
 
  (wfr) CPU A12 -> |06 13| <- CPU D1  (wfr)
 
   (rf) CPU A13 -> |07 12| <- CPU D2  (wfr)
 
   (rf) CPU A13 -> |07 12| <- CPU D2  (wfr)
   (f) CPU A14 -> |08 11| <- nROMSEL (f)
+
   (f) CPU A14 -> |08 11| <- /ROMSEL (f)
           Gnd -- |09 10| -> nIRQ     (f)
+
           Gnd -- |09 10| -> /IRQ    (f)
 +
                  '-----'
 +
 
 +
Kaiser seems to have made a subtle upgrade of the VRC3:
 +
 
 +
National Semiconductor KS202: 20-pin PDIP (canonically [[iNES Mapper 142]])
 +
 
 +
                  .-\_/-.
 +
(wfr) CPU A12 -> |01 20| -> WRAM /CE (w)
 +
  '''(f) CPU A13''' -> |02 19| <- CPU D3  (wfr)
 +
  (f) CPU A14 -> |03 18| <- R/W      (wfr)
 +
          +5V -- |04 17| <- CPU D0  (wfr)
 +
  (f)      M2 -> |05 16| <- CPU D1  (wfr)
 +
  (r) PRG A14 <- |06 15| <- CPU D2  (wfr)
 +
  (r) PRG A13 <- |07 14| -- GND
 +
  (r) PRG A15 <- |08 13| <- /ROMSEL  (f)
 +
  (r) PRG A16 <- |09 12| <- '''RESET'''
 +
  (r) PRG /CE <- |10 11| -> /IRQ     (f)
 
                   '-----'
 
                   '-----'

Revision as of 05:11, 24 September 2019

VRC3: 18-pin PDIP (mapper 73)

r: connects to PRG ROM
f: connects to Famicom
w: connects to PRG RAM
                 .-\_/-.
  (r) PRG A16 <- |01 18| -- +5V
  (r) PRG /CE <- |02 17| -> WRAM /CE (w)
  (r) PRG A14 <- |03 16| <- R/W      (wfr)
  (r) PRG A15 <- |04 15| <- CPU D3   (wfr)
  (f)      M2 -> |05 14| <- CPU D0   (wfr)
(wfr) CPU A12 -> |06 13| <- CPU D1   (wfr)
 (rf) CPU A13 -> |07 12| <- CPU D2   (wfr)
  (f) CPU A14 -> |08 11| <- /ROMSEL  (f)
          Gnd -- |09 10| -> /IRQ     (f)
                 '-----'

Kaiser seems to have made a subtle upgrade of the VRC3:

National Semiconductor KS202: 20-pin PDIP (canonically iNES Mapper 142)

                 .-\_/-.
(wfr) CPU A12 -> |01 20| -> WRAM /CE (w)
  (f) CPU A13 -> |02 19| <- CPU D3   (wfr)
  (f) CPU A14 -> |03 18| <- R/W      (wfr)
          +5V -- |04 17| <- CPU D0   (wfr)
  (f)      M2 -> |05 16| <- CPU D1   (wfr)
  (r) PRG A14 <- |06 15| <- CPU D2   (wfr)
  (r) PRG A13 <- |07 14| -- GND
  (r) PRG A15 <- |08 13| <- /ROMSEL  (f)
  (r) PRG A16 <- |09 12| <- RESET
  (r) PRG /CE <- |10 11| -> /IRQ     (f)
                 '-----'