Difference between revisions of "VRC3 pinout"

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(traced another pinout)
 
m (Protected "VRC3 pinout": Domain migration ([Edit=Allow only administrators] (indefinite)))
 
(8 intermediate revisions by 2 users not shown)
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[[VRC3]]: 18-pin PDIP ([[iNES Mapper 073]])
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{| style="margin: 1em 10%; border: 2px solid #800000; font-size: 200%"
 +
| Nesdev is moving to [//nesdev.org nesdev.org]!
  
r: connects to PRG ROM
+
This page is now at https://wiki.nesdev.org/w/index.php/{{FULLPAGENAMEE}}
f: connects to Famicom
+
|}
w: connects to PRG RAM
 
                  .-\_/-.
 
  (r) PRG A16 <- |01 18| -- +5V
 
  (r) PRG /CE <- |02 17| -> WRAM /CE (w)
 
  (r) PRG A14 <- |03 16| <- CPU RnW (wfr)
 
  (r) PRG A15 <- |04 15| <- CPU D3 (wfr)
 
    (f) CPU M2 -> |05 14| <- CPU D0 (wfr)
 
(wfr) CPU A12 -> |06 13| <- CPU D1 (wfr)
 
  (rf) CPU A13 -> |07 12| <- CPU D2 (wfr)
 
  (f) CPU A14 -> |08 11| <- nROMSEL (f)
 
          Gnd -- |09 10| -> nIRQ
 
                  '-----'
 

Latest revision as of 21:22, 21 September 2021

Nesdev is moving to nesdev.org!

This page is now at https://wiki.nesdev.org/w/index.php/VRC3_pinout